Neuromorphic hardware for somatosensory neuroprostheses

In individuals with sensory-motor impairments, missing limb functions can be restored using neuroprosthetic devices that directly interface with the nervous system. However, restoring the natural tactile experience through electrical neural stimulation requires complex encoding strategies. Indeed, they are presently limited in effectively conveying or restoring tactile sensations by bandwidth constraints. Neuromorphic technology, which mimics the natural behavior of neurons and synapses, holds promise for replicating the encoding of natural touch, potentially informing neurostimulation design. In this perspective, we propose that incorporating neuromorphic technologies into neuroprostheses could be an effective approach for developing more natural human-machine interfaces, potentially leading to advancements in device performance, acceptability, and embeddability. We also highlight ongoing challenges and the required actions to facilitate the future integration of these advanced technologies

A Wireless, High-Voltage Compliant, and Energy-Efficient Visual Intracortical Microstimulator

RÉSUMÉ L’objectif général de ce projet de recherche est la conception, la mise en oeuvre et la validation d’une interface sans fil intracorticale implantable en technologie CMOS avancée pour aider les personnes ayant une déficience visuelle. Les défis majeurs de cette recherche sont de répondre à la conformité à haute tension nécessaire à travers l’interface d’électrode-tissu (IET), augmenter la flexibilité dans la microstimulation et la surveillance multicanale, minimiser le budget de puissance pour un dispositif biomédical implantable, réduire la taille de l’implant et améliorer le taux de transmission sans fil des données. Par conséquent, nous présentons dans cette thèse un système de microstimulation intracorticale multi-puce basée sur une nouvelle architecture pour la transmission des données sans fil et le transfert de l’énergie se servant de couplages inductifs et capacitifs. Une première puce, un générateur de stimuli (SG) éconergétique, et une autre qui est un amplificateur de haute impédance se connectant au réseau de microélectrodes de l’étage de sortie. Les 4 canaux de générateurs de stimuli produisent des impulsions rectangulaires, demi-sinus (DS), plateau-sinus (PS) et autres types d’impulsions de courant à haut rendement énergétique. Le SG comporte un contrôleur de faible puissance, des convertisseurs numérique-analogiques (DAC) opérant en mode courant, générateurs multi-forme d’ondes et miroirs de courants alimentés sous 1.2 et 3.3V se servant pour l’interface entre les deux technologies utilisées. Le courant de stimulation du SG varie entre 2.32 et 220μA pour chaque canal. La deuxième puce (pilote de microélectrodes (MED)), une interface entre le SG et de l’arrangement de microélectrodes (MEA), fournit quatre niveaux différents de courant avec la valeur maximale de 400μA par entrée et 100μA par canal de sortie simultanément pour 8 à 16 sites de stimulation à travers les microélectrodes, connectés soit en configuration bipolaire ou monopolaire. Cette étage de sortie est hautement configurable et capable de délivrer une tension élevée pour satisfaire les conditions de l’interface à travers l’impédance de IET par rapport aux systèmes précédemment rapportés. Les valeurs nominales de plus grandes tensions d’alimentation sont de ±10V. La sortie de tension mesurée est conformément 10V/phase (anodique ou cathodique) pour les tensions d’alimentation spécifiées. L’incrémentation de tensions d’alimentation à ±13V permet de produire un courant de stimulation de 220μA par canal de sortie permettant d’élever la tension de sortie jusqu’au 20V par phase. Cet étage de sortie regroupe un commutateur haute tension pour interfacer une matrice des miroirs de courant (3.3V /20V), un registre à décalage de 32-bits à entrée sérielle, sortie parallèle, et un circuit dédié pour bloquer des états interdits.----------ABSTRACT The general objective of this research project is the design, implementation and validation of an implantable wireless intracortical interface in advanced CMOS technology to aid the visually impaired people. The major challenges in this research are to meet the required highvoltage compliance across electrode-tissue interface (ETI), increase lexibility in multichannel microstimulation and monitoring, minimize power budget for an implantable biomedical device, reduce the implant size, and enhance the data rate in wireless transmission. Therefore, we present in this thesis a multi-chip intracortical microstimulation system based on a novel architecture for wireless data and power transmission comprising inductive and capacitive couplings. The first chip is an energy-efficient stimuli generator (SG) and the second one is a highimpedance microelectrode array driver output-stage. The 4-channel stimuli-generator produces rectangular, half-sine (HS), plateau-sine (PS), and other types of energy-efficient current pulse. The SG is featured with low-power controller, current mode source- and sinkdigital- to-analog converters (DACs), multi-waveform generators, and 1.2V/3.3V interface current mirrors. The stimulation current per channel of the SG ranges from 2.32 to 220μA per channel. The second chip (microelectrode driver (MED)), an interface between the SG and the microelectrode array (MEA), supplies four different current levels with the maximum value of 400μA per input and 100μA per output channel. These currents can be delivered simultaneously to 8 to 16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. This output stage is highly-configurable and able to deliver higher compliance voltage across ETI impedance compared to previously reported designs. The nominal values of largest supply voltages are ±10V. The measured output compliance voltage is 10V/phase (anodic or cathodic) for the specified supply voltages. Increment of supply voltages to ±13V allows 220μA stimulation current per output channel enhancing the output compliance voltage up to 20V per phase. This output-stage is featured with a high-voltage switch-matrix, 3.3V/20V current mirrors, an on-chip 32-bit serial-in parallel-out shift register, and the forbidden state logic building blocks. The SG and MED chips have been designed and fabricated in IBM 0.13μm CMOS and Teledyne DALSA 0.8μm 5V/20V CMOS/DMOS technologies with silicon areas occupied by them 1.75 x 1.75mm2 and 4 x 4mm2 respectively. The measured DC power budgets consumed by low-and mid-voltage microchips are 2.56 and 2.1mW consecutively

An optogenetic headstage for optical stimulation and neural recording in life science applications

L'optogénétique est une nouvelle méthode de contrôle de l’activité neuronale dans laquelle la lumière est employée pour activer ou arrêter certains neurones. Dans le cadre de ce travail, un dispositif permettant l’acquisition de signaux neuronaux et conduisant à une stimulation optogénétique de façon multicanale et temps-réel a été conçu. Cet outil est muni de deux canaux de stimulation optogénétique et de deux canaux de lecture des signaux neuronaux. La source de lumière est une DEL qui peut consommer jusqu’à 150 milliampères. Les signaux neuronaux acquis sont transmis à un ordinateur par une radio. Les dimensions sont d’environ 20×20×15 mm3 et le poids est de moins de 7 grammes, rendant l’appareil utile pour les expériences sur les petits animaux libres. Selon nos connaissances actuelles, le résultat de ce projet constitue le premier appareil de recherche optogénétique sans-fil, compact offrant la capture de signaux cérébraux et la stimulation optique simultanée.Optogenetics is a new method for controlling the neural activity where light is used to activate or silence, with high spatial and temporal resolution, genetically light-sensitized neurons. In optogenetics, a light source such as a LED, targets light-sensitized neurons. In this work, a light-weight wireless animal optogenetic headstage has been designed that allows multi-channel simultaneous real-time optical stimulation and neural recording. This system has two optogenetic stimulation channels and two electrophysiological reading channels. The optogenetic stimulation channels benefit from high-power LEDs (sinking 150 milliamps) with flexible stimulation patterns and the recorded neural data is wirelessly sent to a computer. The dimensions of the headstage are almost 20×20×15 mm3 and it weighs less than 7 grams. This headstage is suitable for tests on small freely-moving rodents. To the best of our knowledge, this is the first reported fully wireless headstage to offer simultaneous multichannel optical stimulation along with multichannel neural recording capability

Otimização do fronthaul ótico para redes de acesso de rádio (baseadas) em computação em nuvem (CC-RANs)

Doutoramento conjunto (MAP-Tele) em Engenharia Eletrotécnica/TelecomunicaçõesA proliferação de diversos tipos de dispositivos moveis, aplicações e serviços com grande necessidade de largura de banda têm contribuído para o aumento de ligações de banda larga e ao aumento do volume de trafego das redes de telecomunicações moveis. Este aumento exponencial tem posto uma enorme pressão nos mobile operadores de redes móveis (MNOs). Um dos aspetos principais deste recente desenvolvimento, é a necessidade que as redes têm de oferecer baixa complexidade nas ligações, como também baixo consumo energético, muito baixa latência e ao mesmo tempo uma grande capacidade por baixo usto. De maneira a resolver estas questões, os MNOs têm focado a sua atenção na redes de acesso por rádio em nuvem (C-RAN) principalmente devido aos seus benefícios em termos de otimização de performance e relação qualidade preço. O standard para a distribuição de sinais sem fios por um fronthaul C-RAN é o common public radio interface (CPRI). No entanto, ligações óticas baseadas em interfaces CPRI necessitam de uma grande largura de banda. Estes requerimentos podem também ser atingidos com uma implementação em ligação free space optical (FSO) que é um sistema ótico que usa comunicação sem fios. O FSO tem sido uma alternativa muito apelativa aos sistemas de comunicação rádio (RF) pois combinam a flexibilidade e mobilidade das redes RF ao mesmo tempo que permitem a elevada largura de banda permitida pelo sistema ótico. No entanto, as ligações FSO são suscetíveis a alterações atmosféricas que podem prejudicar o desempenho do sistema de comunicação. Estas limitações têm evitado o FSO de ser tornar uma excelente solução para o fronthaul. Uma caracterização precisa do canal e tecnologias mais avançadas são então necessárias para uma implementação pratica de ligações FSO. Nesta tese, vamos estudar uma implementação eficiente para fronthaul baseada em tecnologia á rádio-sobre-FSO (RoFSO). Propomos expressões em forma fechada para mitigação das perdas de propagação e para a estimação da capacidade do canal de maneira a aliviar a complexidade do sistema de comunicação. Simulações numéricas são também apresentadas para formatos de modulação adaptativas. São também considerados esquemas como um sistema hibrido RF/FSO e tecnologias de transmissão apoiadas por retransmissores que ajudam a alivar os requerimentos impostos por um backhaul/fronthaul de C-RAN. Os modelos propostos não só reduzem o esforço computacional, como também têm outros méritos, tais como, uma elevada precisão na estimação do canal e desempenho, baixo requisitos na capacidade de memória e uma rápida e estável operação comparativamente com o estado da arte em sistemas analíticos (PON)-FSO. Este sistema é implementado num recetor em tempo real que é emulado através de uma field-programmable gate array (FPGA) comercial. Permitindo assim um sistema aberto, interoperabilidade, portabilidade e também obedecer a standards de software aberto. Os esquemas híbridos têm a habilidade de suportar diferentes aplicações, serviços e múltiplos operadores a partilharem a mesma infraestrutura de fibra ótica.The proliferation of different mobile devices, bandwidth-intensive applications and services contribute to the increase in the broadband connections and the volume of traffic on the mobile networks. This exponential growth has put considerable pressure on the mobile network operators (MNOs). In principal, there is a need for networks that not only offer low-complexity, low-energy consumption, and extremely low-latency but also high-capacity at relatively low cost. In order to address the demand, MNOs have given significant attention to the cloud radio access network (C-RAN) due to its beneficial features in terms of performance optimization and cost-effectiveness. The de facto standard for distributing wireless signal over the C-RAN fronthaul is the common public radio interface (CPRI). However, optical links based on CPRI interfaces requires large bandwidth. Also, the aforementioned requirements can be realized with the implementation of free space optical (FSO) link, which is an optical wireless system. The FSO is an appealing alternative to the radio frequency (RF) communication system that combines the flexibility and mobility offered by the RF networks with the high-data rates provided by the optical systems. However, the FSO links are susceptible to atmospheric impairments which eventually hinder the system performance. Consequently, these limitations prevent FSO from being an efficient standalone fronthaul solution. So, precise channel characterizations and advanced technologies are required for practical FSO link deployment and operation. In this thesis, we study an efficient fronthaul implementation that is based on radio-on-FSO (RoFSO) technologies. We propose closedform expressions for fading-mitigation and for the estimation of channel capacity so as to alleviate the system complexity. Numerical simulations are presented for adaptive modulation scheme using advanced modulation formats. We also consider schemes like hybrid RF/FSO and relay-assisted transmission technologies that can help in alleviating the stringent requirements by the C-RAN backhaul/fronthaul. The propose models not only reduce the computational requirements/efforts, but also have a number of diverse merits such as high-accuracy, low-memory requirements, fast and stable operation compared to the current state-of-the-art analytical based approaches. In addition to the FSO channel characterization, we present a proof-of-concept experiment in which we study the transmission capabilities of a hybrid passive optical network (PON)-FSO system. This is implemented with the real-time receiver that is emulated by a commercial field-programmable gate array (FPGA). This helps in facilitating an open system and hence enables interoperability, portability, and open software standards. The hybrid schemes have the ability to support different applications, services, and multiple operators over a shared optical fiber infrastructure

Development of a Full-Field Time-of-Flight Range Imaging System

A full-field, time-of-flight, image ranging system or 3D camera has been developed from a proof-of-principle to a working prototype stage, capable of determining the intensity and range for every pixel in a scene. The system can be adapted to the requirements of various applications, producing high precision range measurements with sub-millimetre resolution, or high speed measurements at video frame rates. Parallel data acquisition at each pixel provides high spatial resolution independent of the operating speed. The range imaging system uses a heterodyne technique to indirectly measure time of flight. Laser diodes with highly diverging beams are intensity modulated at radio frequencies and used to illuminate the scene. Reflected light is focused on to an image intensifier used as a high speed optical shutter, which is modulated at a slightly different frequency to that of the laser source. The output from the shutter is a low frequency beat signal, which is sampled by a digital video camera. Optical propagation delay is encoded into the phase of the beat signal, hence from a captured time variant intensity sequence, the beat signal phase can be measured to determine range for every pixel in the scene. A direct digital synthesiser (DDS) is designed and constructed, capable of generating up to three outputs at frequencies beyond 100 MHz with the relative frequency stability in excess of nine orders of magnitude required to control the laser and shutter modulation. Driver circuits were also designed to modulate the image intensifier photocathode at 50 Vpp, and four laser diodes with a combined power output of 320 mW, both over a frequency range of 10-100 MHz. The DDS, laser, and image intensifier response are characterised. A unique method of measuring the image intensifier optical modulation response is developed, requiring the construction of a pico-second pulsed laser source. This characterisation revealed deficiencies in the measured responses, which were mitigated through hardware modifications where possible. The effects of remaining imperfections, such as modulation waveform harmonics and image intensifier irising, can be calibrated and removed from the range measurements during software processing using the characterisation data. Finally, a digital method of generating the high frequency modulation signals using a FPGA to replace the analogue DDS is developed, providing a highly integrated solution, reducing the complexity, and enhancing flexibility. In addition, a novel modulation coding technique is developed to remove the undesirable influence of waveform harmonics from the range measurement without extending the acquisition time. When combined with a proposed modification to the laser illumination source, the digital system can enhance range measurement precision and linearity. From this work, a flexible full-field image ranging system is successfully realised. The system is demonstrated operating in a high precision mode with sub-millimetre depth resolution, and also in a high speed mode operating at video update rates (25 fps), in both cases providing high (512 512) spatial resolution over distances of several metres

Techniques of design optimisation for algorithms implemented in software

The overarching objective of this thesis was to develop tools for parallelising, optimising, and implementing algorithms on parallel architectures, in particular General Purpose Graphics Processors (GPGPUs). Two projects were chosen from different application areas in which GPGPUs are used: a defence application involving image compression, and a modelling application in bioinformatics (computational immunology). Each project had its own specific objectives, as well as supporting the overall research goal. The defence / image compression project was carried out in collaboration with the Jet Propulsion Laboratories. The specific questions were: to what extent an algorithm designed for bit-serial for the lossless compression of hyperspectral images on-board unmanned vehicles (UAVs) in hardware could be parallelised, whether GPGPUs could be used to implement that algorithm, and whether a software implementation with or without GPGPU acceleration could match the throughput of a dedicated hardware (FPGA) implementation. The dependencies within the algorithm were analysed, and the algorithm parallelised. The algorithm was implemented in software for GPGPU, and optimised. During the optimisation process, profiling revealed less than optimal device utilisation, but no further optimisations resulted in an improvement in speed. The design had hit a local-maximum of performance. Analysis of the arithmetic intensity and data-flow exposed flaws in the standard optimisation metric of kernel occupancy used for GPU optimisation. Redesigning the implementation with revised criteria (fused kernels, lower occupancy, and greater data locality) led to a new implementation with 10x higher throughput. GPGPUs were shown to be viable for on-board implementation of the CCSDS lossless hyperspectral image compression algorithm, exceeding the performance of the hardware reference implementation, and providing sufficient throughput for the next generation of image sensor as well. The second project was carried out in collaboration with biologists at the University of Arizona and involved modelling a complex biological system – VDJ recombination involved in the formation of T-cell receptors (TCRs). Generation of immune receptors (T cell receptor and antibodies) by VDJ recombination is an enormously complex process, which can theoretically synthesize greater than 1018 variants. Originally thought to be a random process, the underlying mechanisms clearly have a non-random nature that preferentially creates a small subset of immune receptors in many individuals. Understanding this bias is a longstanding problem in the field of immunology. Modelling the process of VDJ recombination to determine the number of ways each immune receptor can be synthesized, previously thought to be untenable, is a key first step in determining how this special population is made. The computational tools developed in this thesis have allowed immunologists for the first time to comprehensively test and invalidate a longstanding theory (convergent recombination) for how this special population is created, while generating the data needed to develop novel hypothesis

Short term plasticity. A neuromorphic perspective

Ramachandran H. Short term plasticity. A neuromorphic perspective. Bielefeld: Universität Bielefeld; 2018

Development of a CMOS A/D Converter for an Artificial Synapse

This thesis deals with background, theory, design, layout and experimental test results of an analogue CMOS VLSI current-mode analog-to-digital converter. This system supports a project, whose goal it is to build a biologically relevant model of synaptic plasticity, named the Artificial Synapse. A critical part of the design, which is based on analogue CMOS VLSI circuits, is the ability to activate a discrete number of channels by sampling an analogue signal. Since currents are the signal of interest and transistors are biased in weak inversion (subthreshold regime), the system requires a current mode A/D circuit that it can operate at ultra-low power and current levels. To meet this need, two new innovative A/D converter approaches are proposed to replace the system’s previous A/D converter design which suffered from a non-linear resolution, uncoded output code and heavy bit oscillations. The initial technical requirements and key criteria for the new converter comprise a resolution of one nano ampere, an input current range between 0 – 100nA, conversion frequencies of up to 5kHz, and a power supply voltage of less than 1.5V. Temperature range, space occupation and power dissipation aspects were not specified due to the early stage of the related Artificial Synapse project. The novel converters both produce seven bit thermometer codes, their functional principle can be best described as current mode flash analog-to-digital converters (ADCs). Due to the fact that the input signal is in the area of a subthreshold current, it is selfevident that the A/D converter design should operate at a subthreshold realm. To support low power operation, clocks or high currents could not be used and were excluded from the design from the very start. To encode the thermometer code into standard binary code, a seven-to-three encoder was designed and integrated on the chip. In October 2003, the design was submitted for production to the MOSIS circuit fabrication service. The AMI Semiconductor 1.5 micron ABN CMOS process was chosen to manufacture the chip. When it was returned in January 2004, simulation results showed that both new A/D converter approaches accomplished excellent results which were expected from SPICE simulation results. With the new chip installed, it became possible to resolve input currents as small as one nano ampere and achieve conversion frequencies of up to 5kHz. The circuits also both meet the requirements which were set at the beginning of the project to operate at a power supply voltage of less than 1.5V, processing input currents in the range between 0 – 100nA. A prototype printed circuit board (PCB) was developed, produced and employed for experiments with the chip. The major application of this test-bed is the ability to generate and measure extremely low currents with high precision. This enables the monitoring of the very small currents that are processed by the chip

Personality Identification from Social Media Using Deep Learning: A Review

Social media helps in sharing of ideas and information among people scattered around the world and thus helps in creating communities, groups, and virtual networks. Identification of personality is significant in many types of applications such as in detecting the mental state or character of a person, predicting job satisfaction, professional and personal relationship success, in recommendation systems. Personality is also an important factor to determine individual variation in thoughts, feelings, and conduct systems. According to the survey of Global social media research in 2018, approximately 3.196 billion social media users are in worldwide. The numbers are estimated to grow rapidly further with the use of mobile smart devices and advancement in technology. Support vector machine (SVM), Naive Bayes (NB), Multilayer perceptron neural network, and convolutional neural network (CNN) are some of the machine learning techniques used for personality identification in the literature review. This paper presents various studies conducted in identifying the personality of social media users with the help of machine learning approaches and the recent studies that targeted to predict the personality of online social media (OSM) users are reviewed