Onboard processing of synthetic aperture radar backprojection algorithm in FPGA

Synthetic aperture radar is a microwave technique to extracting image information of the target. Electromagnetic waves that are reflected from the target are acquired by the aircraft or satellite receivers and sent to a ground station to be processed by applying computational demanding algorithms. Radar data streams are acquired by an aircraft or satellite and sent to a ground station to be processed in order to extract images from the data since these processing algorithms are computationally demanding. However, novel applications require real-time processing for real-time analysis and decisions and so onboard processing is necessary. Running computationally demanding algorithms on onboard embedded systems with limited energy and computational capacity is a challenge. This article proposes a configurable hardware core for the execution of the backprojection algorithm with high performance and energy efficiency. The original backprojection algorithm is restructured to expose computational parallelism and then optimized by replacing floating-point with fixed-point arithmetic. The backprojection core was integrated into a system-onchip architecture and implemented in a field-programmable gate array. The proposed solution runs the optimized backprojection algorithm over images of sizes 512 x 512 and 1024 x 1024 in 0.14 s (0.41 J) and 1.11 s (3.24 J), respectively. The architecture is 2.6x faster and consumes 13x less energy than an embedded Jetson TX2 GPU. The solution is scalable and, therefore, a tradeoff exists between performance and utilization of resources.info:eu-repo/semantics/publishedVersio

Reconfigurable L-Band Radar

The reconfigurable L-Band radar is an ongoing development at NASA/GSFC that exploits the capability inherently in phased array radar systems with a state-of-the-art data acquisition and real-time processor in order to enable multi-mode measurement techniques in a single radar architecture. The development leverages on the L-Band Imaging Scatterometer, a radar system designed for the development and testing of new radar techniques; and the custom-built DBSAR processor, a highly reconfigurable, high speed data acquisition and processing system. The radar modes currently implemented include scatterometer, synthetic aperture radar, and altimetry; and plans to add new modes such as radiometry and bi-static GNSS signals are being formulated. This development is aimed at enhancing the radar remote sensing capabilities for airborne and spaceborne applications in support of Earth Science and planetary exploration This paper describes the design of the radar and processor systems, explains the operational modes, and discusses preliminary measurements and future plans

Advances in Sensors-Centric Microprocessors and System-on-Chip

sensor

High-Performance Computing for SKA Transient Search: Use of FPGA based Accelerators -- a brief review

This paper presents the High-Performance computing efforts with FPGA for the accelerated pulsar/transient search for the SKA. Case studies are presented from within SKA and pathfinder telescopes highlighting future opportunities. It reviews the scenario that has shifted from offline processing of the radio telescope data to digitizing several hundreds/thousands of antenna outputs over huge bandwidths, forming several 100s of beams, and processing the data in the SKA real-time pulsar search pipelines. A brief account of the different architectures of the accelerators, primarily the new generation Field Programmable Gate Array-based accelerators, showing their critical roles to achieve high-performance computing and in handling the enormous data volume problems of the SKA is presented here. It also presents the power-performance efficiency of this emerging technology and presents potential future scenarios.Comment: Accepted for JoAA, SKA Special issue on SKA (2022

A Real-time SAR Echo Simulator Based on FPGA and Parallel Computing

This paper designs and implements a SAR (Synthetic Aperture Radar) real-time echo simulator based on multi-FPGA parallel computing. The one-dimensional frequency-domain Fourier transform algorithm is used in the simulator, and the echo signal model and the rapid calculation algorithm of impulse response function are introduced. The pipeline compute structure, multichannel parallel computing and procedure flow design are the key technologies of the simulator, which are also presented in details. And finally, the validity and correctness of the SAR echo simulator are verified through the imaging results of the point-array target and the nature scene target

Aggregation of Descriptive Regularization Methods with Hardware/Software Co-Design for Remote Sensing Imaging

This study consider the problem of high-resolution imaging of the remote sensing (RS) environment formalized in terms of a nonlinear ill- posed inverse problem of nonparametric estimation of the power spatial spectrum pattern (SSP) of the wavefield scattered from an extended remotely sensed scene (referred to as the scene image). However, the remote sensing techniques for reconstructive imaging in many RS application areas are relatively unacceptable for being implemented in a (near) real time implementation. In this work, we address a new aggregated descriptive-regularization (DR) method and the Hardware/Software (HW/SW) co-design for the SSP reconstruction from the uncertain speckle-corrupted measurement data in a computationally efficient parallel fashion that meets the (near) real time image processing requirements. The hardware design is performed via efficient systolic arrays (SAs). Finally, the efficiency both in resolution enhancement and in computational complexity reduction metrics of the aggregated descriptive-regularized and the HW/SW co-design method is presented via numerical simulations and by the performance analysis of the implementation based on a Xilinx Field Programmable Gate Array (FPGA) XC4VSX35-10ff668.Universidad de GuadalajaraUniversidad Autónoma de YucatánInstituto Tecnológico de Mérid

EO-Alert: A Satellite Architecture for Detection and Monitoring of Extreme Events in Real Time

This paper presents the architecture and results achieved by the EO-ALERT H2020 project. EO-ALERT proposes the definition and development of the next-generation Earth Observation (EO) data processing chain, based on a novel flight segment architecture that moves optimised key EO data processing elements from the ground segment to onboard the satellite, with the aim of delivering the EO products to the end user with very low latency (in almost real-time). This paper presents the EO-ALERT architecture, its performance and hardware. Performances are presented for two reference user scenarios; ship detection and extreme weather nowcasting/monitoring. The hardware testing results show that, when implemented using Commercial Off-The-Shelf (COTS) components and available communication links, the proposed architecture can deliver EO products and alerts to the end user with a latency lower than one-point-five minutes, for both SAR and Optical Very High Resolution (VHR) missions, demonstrating the viability of the EO-ALERT concept and architecture

EO-ALERT: A Novel Architecture for the Next Generation of Earth Observation Satellites Supporting Rapid Civil Alerts

Satellite Earth Observation (EO) data is ubiquitously used in many applications, providing basic services to society, such as environment monitoring, emergency management and civilian security. Due to the increasing request of EO products by the market, the classical EO data chain generates a severe bottleneck problem, further exacerbated in constellations. A huge amount of EO raw data generated on-board the satellite must be transferred to ground, slowing down the EO product availability, increasing latency, and hampering the growth of applications in accordance with the increased user demand. This paper provides an overview of the results achieved by the EO-ALERT project (http://eo-alert-h2020.eu/), an H2020 European Union research activity led by DEIMOS Space. EO-ALERT proposes the definition and development of the next-generation EO data processing chain, based on a novel flight segment architecture that moves optimised key EO data processing elements from the ground segment to on-board the satellite, with the aim of delivering the EO products to the end user with very low latency (quasi-real-time). EO-ALERT achieves, globally, latencies below five minutes for EO products delivery, reaching latencies below 1 minute in some scenarios. The proposed architecture solves the above challenges through a combination of innovations in the on-board elements of the data chain and the communications. Namely, the architecture introduces innovative technological solutions, including on-board reconfigurable data handling, on-board image generation and processing for the generation of alerts (EO products) using Artificial Intelligence (AI), on-board data compression and encryption using AI, high-speed on-board avionics, and reconfigurable high data rate communication links to ground, including a separate chain for alerts with minimum latency and global coverage. The paper presents the proposed architecture, its performance and hardware, considering two different user scenarios; ship detection and extreme weather observation/nowcasting. The results show that, when implemented using COTS components and available communication links, the proposed architecture can deliver alerts to ground with latency lower than five minutes, for both SAR and Optical missions, demonstrating the viability of the EOALERT concept and architecture. The paper also discusses the implementation on an avionics test bench for testing the architecture with real EO data, with the aim of demonstrating that it can meet the requirements of the considered scenarios in terms of detection performance and provides technologies at a high TRL (4-5). When proven, this will open unprecedented opportunities for the exploitation of civil EO products, especially in latency sensitive scenarios, such as disaster management