FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

H-SIMD machine : configurable parallel computing for data-intensive applications

This dissertation presents a hierarchical single-instruction multiple-data (H-SLMD) configurable computing architecture to facilitate the efficient execution of data-intensive applications on field-programmable gate arrays (FPGAs). H-SIMD targets data-intensive applications for FPGA-based system designs. The H-SIMD machine is associated with a hierarchical instruction set architecture (HISA) which is developed for each application. The main objectives of this work are to facilitate ease of program development and high performance through ease of scheduling operations and overlapping communications with computations. The H-SIMD machine is composed of the host, FPGA and nano-processor layers. They execute host SIMD instructions (HSIs), FPGA SIMD instructions (FSIs) and nano-processor instructions (NPLs), respectively. A distinction between communication and computation instructions is intended for all the HISA layers. The H-SIMD machine also employs a memory switching scheme to bridge the omnipresent large bandwidth gaps in configurable systems. To showcase the proposed high-performance approach, the conditions to fully overlap communications with computations are investigated for important applications. The building blocks in the H-SLMD machine, such as high-performance and area-efficient register files, are presented in detail. The H-SLMD machine hierarchy is implemented on a host Dell workstation and the Annapolis Wildstar II FPGA board. Significant speedups have been achieved for matrix multiplication (MM), 2-dimensional discrete cosine transform (2D DCT) and 2-dimensional fast Fourier transform (2D FFT) which are used widely in science and engineering. In another FPGA-based programming paradigm, a high-level language (here ANSI C) can be used to program the FPGAs in a mode similar to that of the H-SIMD machine in terms of trying to minimize the effect of overheads. More specifically, a multi-threaded overlapping scheme is proposed to reduce as much as possible, or even completely hide, runtime FPGA reconfiguration overheads. Nevertheless, although the HLL-enabled reconfigurable machine allows software developers to customize FPGA functions easily, special architecture techniques are needed to achieve high-performance without significant penalty on area and clock frequency. Two important high-performance applications, matrix multiplication and image edge detection, are tested on the SRC-6 reconfigurable machine. The implemented algorithms are able to exploit the available data parallelism with independent functional units and application-specific cache support. Relevant performance and design tradeoffs are analyzed

FPGAs in Industrial Control Applications

The aim of this paper is to review the state-of-the-art of Field Programmable Gate Array (FPGA) technologies and their contribution to industrial control applications. Authors start by addressing various research fields which can exploit the advantages of FPGAs. The features of these devices are then presented, followed by their corresponding design tools. To illustrate the benefits of using FPGAs in the case of complex control applications, a sensorless motor controller has been treated. This controller is based on the Extended Kalman Filter. Its development has been made according to a dedicated design methodology, which is also discussed. The use of FPGAs to implement artificial intelligence-based industrial controllers is then briefly reviewed. The final section presents two short case studies of Neural Network control systems designs targeting FPGAs

Robust fault tolerant control of induction motor system

Research into fault tolerant control (FTC, a set of techniques that are developed to increase plant availability and reduce the risk of safety hazards) for induction motors is motivated by practical concerns including the need for enhanced reliability, improved maintenance operations and reduced cost. Its aim is to prevent that simple faults develop into serious failure. Although, the subject of induction motor control is well known, the main topics in the literature are concerned with scalar and vector control and structural stability. However, induction machines experience various fault scenarios and to meet the above requirements FTC strategies based on existing or more advanced control methods become desirable. Some earlier studies on FTC have addressed particular problems of 3-phase sensor current/voltage FTC, torque FTC, etc. However, the development of these methods lacks a more general understanding of the overall problem of FTC for an induction motor based on a true fault classification of possible fault types.In order to develop a more general approach to FTC for induction motors, i.e. not just designing specific control approaches for individual induction motor fault scenarios, this thesis has carried out a systematic research on induction motor systems considering the various faults that can typically be present, having either “additive” fault or “multiplicative” effects on the system dynamics, according to whether the faults are sensor or actuator (additive fault) types or component or motor faults (multiplicative fault) types.To achieve the required objectives, an active approach to FTC is used, making use of fault estimation (FE, an approach that determine the magnitude of a fault signal online) and fault compensation. This approach of FTC/FE considers an integration of the electrical and mechanical dynamics, initially using adaptive and/or sliding mode observers, Linear Parameter Varying (LPV, in which nonlinear systems are locally decomposed into several linear systems scheduled by varying parameters) and then using back-stepping control combined with observer/estimation methods for handling certain forms of nonlinearity.In conclusion, the thesis proposed an integrated research of induction motor FTC/FE with the consideration of different types of faults and different types of uncertainties, and validated the approaches through simulations and experiments

Enhancing Real-time Embedded Image Processing Robustness on Reconfigurable Devices for Critical Applications

Nowadays, image processing is increasingly used in several application fields, such as biomedical, aerospace, or automotive. Within these fields, image processing is used to serve both non-critical and critical tasks. As example, in automotive, cameras are becoming key sensors in increasing car safety, driving assistance and driving comfort. They have been employed for infotainment (non-critical), as well as for some driver assistance tasks (critical), such as Forward Collision Avoidance, Intelligent Speed Control, or Pedestrian Detection. The complexity of these algorithms brings a challenge in real-time image processing systems, requiring high computing capacity, usually not available in processors for embedded systems. Hardware acceleration is therefore crucial, and devices such as Field Programmable Gate Arrays (FPGAs) best fit the growing demand of computational capabilities. These devices can assist embedded processors by significantly speeding-up computationally intensive software algorithms. Moreover, critical applications introduce strict requirements not only from the real-time constraints, but also from the device reliability and algorithm robustness points of view. Technology scaling is highlighting reliability problems related to aging phenomena, and to the increasing sensitivity of digital devices to external radiation events that can cause transient or even permanent faults. These faults can lead to wrong information processed or, in the worst case, to a dangerous system failure. In this context, the reconfigurable nature of FPGA devices can be exploited to increase the system reliability and robustness by leveraging Dynamic Partial Reconfiguration features. The research work presented in this thesis focuses on the development of techniques for implementing efficient and robust real-time embedded image processing hardware accelerators and systems for mission-critical applications. Three main challenges have been faced and will be discussed, along with proposed solutions, throughout the thesis: (i) achieving real-time performances, (ii) enhancing algorithm robustness, and (iii) increasing overall system's dependability. In order to ensure real-time performances, efficient FPGA-based hardware accelerators implementing selected image processing algorithms have been developed. Functionalities offered by the target technology, and algorithm's characteristics have been constantly taken into account while designing such accelerators, in order to efficiently tailor algorithm's operations to available hardware resources. On the other hand, the key idea for increasing image processing algorithms' robustness is to introduce self-adaptivity features at algorithm level, in order to maintain constant, or improve, the quality of results for a wide range of input conditions, that are not always fully predictable at design-time (e.g., noise level variations). This has been accomplished by measuring at run-time some characteristics of the input images, and then tuning the algorithm parameters based on such estimations. Dynamic reconfiguration features of modern reconfigurable FPGA have been extensively exploited in order to integrate run-time adaptivity into the designed hardware accelerators. Tools and methodologies have been also developed in order to increase the overall system dependability during reconfiguration processes, thus providing safe run-time adaptation mechanisms. In addition, taking into account the target technology and the environments in which the developed hardware accelerators and systems may be employed, dependability issues have been analyzed, leading to the development of a platform for quickly assessing the reliability and characterizing the behavior of hardware accelerators implemented on reconfigurable FPGAs when they are affected by such faults

Induction Motors

AC motors play a major role in modern industrial applications. Squirrel-cage induction motors (SCIMs) are probably the most frequently used when compared to other AC motors because of their low cost, ruggedness, and low maintenance. The material presented in this book is organized into four sections, covering the applications and structural properties of induction motors (IMs), fault detection and diagnostics, control strategies, and the more recently developed topology based on the multiphase (more than three phases) induction motors. This material should be of specific interest to engineers and researchers who are engaged in the modeling, design, and implementation of control algorithms applied to induction motors and, more generally, to readers broadly interested in nonlinear control, health condition monitoring, and fault diagnosis

A study of FPGA-based System-on-Chip designs for real-time industrial application

This paper shows the benefits of the Field Programming Gate Array (FPGAs) in industrial control applications. The author starts by addressing the benefits of FPGA and where it is useful. As well as, the author has done some FPGA’s evaluation researches on the FPGA performing explaining the performance of the FPGA and the design tools. To show the benefits of the FPGA, an industrial application example has been used. The application is a real-time face detection and tracking using FPGA. Face tracking will depend on calculating the centroid of each detected region. A DE2-SoC Altera board has been used to implement this application. The application based on few algorithms that filter the captured images to detect them. These algorithms have been translated to a Verilog code to run it on the DE2-SoC boar

Field weakening and sensorless control solutions for synchronous machines applied to electric vehicles.

184 p.La polución es uno de los mayores problemas en los países industrializados. Por ello, la electrificación del transporte por carretera está en pleno auge, favoreciendo la investigación y el desarrollo industrial. El desarrollo de sistemas de propulsión eficientes, fiables, compactos y económicos juega un papel fundamental para la introducción del vehículo eléctrico en el mercado.Las máquinas síncronas de imanes permanentes son, a día de hoy la tecnología más empleada en vehículos eléctricos e híbridos por sus características. Sin embargo, al depender del uso de tierras raras, se están investigando alternativas a este tipo de máquina, tales como las máquinas de reluctancia síncrona asistidas por imanes. Para este tipo de máquinas síncronas es necesario desarrollar estrategias de control eficientes y robustas. Las desviaciones de parámetros son comunes en estas máquinas debido a la saturación magnética y a otra serie de factores, tales como tolerancias de fabricación, dependencias en función de la temperatura de operación o envejecimiento. Las técnicas de control convencionales, especialmente las estrategias de debilitamiento de campo dependen, en general, del conocimiento previo de dichos parámetros. Si no son lo suficientemente robustos, pueden producir problemas de control en las regiones de debilitamiento de campo y debilitamiento de campo profundo. En este sentido, esta tesis presenta dos nuevas estrategias de control de debilitamiento de campo híbridas basadas en LUTs y reguladores VCT.Por otro lado, otro requisito indispensable para la industria de la automoción es la detección de faltas y la tolerancia a fallos. En este sentido, se presenta una nueva estrategia de control sensorless basada en una estructura PLL/HFI híbrida que permite al vehículo continuar operando de forma pseudo-óptima ante roturas en el sensor de posición y velocidad de la máquina eléctrica. En esta tesis, ambas propuestas se validan experimentalmente en un sistema de propulsión real para vehículo eléctrico que cuenta con una máquina de reluctancia síncrona asistidas por imanes de 51 kW

A Framework for the Design and Analysis of High-Performance Applications on FPGAs using Partial Reconfiguration

The field-programmable gate array (FPGA) is a dynamically reconfigurable digital logic chip used to implement custom hardware. The large densities of modern FPGAs and the capability of the on-thely reconfiguration has made the FPGA a viable alternative to fixed logic hardware chips such as the ASIC. In high-performance computing, FPGAs are used as co-processors to speed up computationally intensive processes or as autonomous systems that realize a complete hardware application. However, due to the limited capacity of FPGA logic resources, denser FPGAs must be purchased if more logic resources are required to realize all the functions of a complex application. Alternatively, partial reconfiguration (PR) can be used to swap, on demand, idle components of the application with active components. This research uses PR to swap components to improve the performance of the application given the limited logic resources available with smaller but economical FPGAs. The swap is called ”resource sharing PR”. In a pipelined design of multiple hardware modules (pipeline stages), resource sharing PR is a technique that uses PR to improve the performance of pipeline bottlenecks. This is done by reconfiguring other pipeline stages, typically those that are idle waiting for data from a bottleneck, into an additional parallel bottleneck module. The target pipeline of this research is a two-stage “slow-toast” pipeline where the flow of data traversing the pipeline transitions from a relatively slow, bottleneck stage to a fast stage. A two stage pipeline that combines FPGA-based hardware implementations of well-known Bioinformatics search algorithms, the X! Tandem algorithm and the Smith-Waterman algorithm, is implemented for this research; the implemented pipeline demonstrates that characteristics of these algorithm. The experimental results show that, in a database of unknown peptide spectra, when matching spectra with 388 peaks or greater, performing resource sharing PR to instantiate a parallel X! Tandem module is worth the cost for PR. In addition, from timings gathered during experiments, a general formula was derived for determining the value of performing PR upon a fast module