5,986 research outputs found
First prototype of a silicon tracker using an artificial retina for fast track finding
We report on the R\&D for a first prototype of a silicon tracker based on an
alternative approach for fast track finding. The working principle is inspired
from neurobiology, in particular by the processing of visual images by the
brain as it happens in nature. It is based on extensive parallelisation of data
distribution and pattern recognition. In this work we present the design of a
practical device that consists of a telescope based on single-sided silicon
detectors; we describe the data acquisition system and the implementation of
the track finding algorithms using available digital logic of commercial FPGA
devices. Tracking performance and trigger capabilities of the device are
discussed along with perspectives for future applications.Comment: 9 pages, 7 figures, Technology and Instrumentation in Particle
Physics 2014 (TIPP 2014), conference proceeding
The first version Buffered Large Analog Bandwidth (BLAB1) ASIC for high luminosity collider and extensive radio neutrino detectors
Future detectors for high luminosity particle identification and ultra high
energy neutrino observation would benefit from a digitizer capable of recording
sensor elements with high analog bandwidth and large record depth, in a
cost-effective, compact and low-power way. A first version of the Buffered
Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons
learned from the development of the Large Analog Bandwidth Recorder and
Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has
been very successful and forms the basis of a generation of new, large-scale
radio neutrino detectors, its limited sampling depth is a major drawback. A
prototype has been designed and fabricated with 65k deep sampling at
multi-GSa/s operation. We present test results and directions for future
evolution of this sampling technique.Comment: 15 pages, 26 figures; revised, accepted for publication in NIM
Programmable flexible cores for SoC applications
Tese de mestrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200
HardScope: Thwarting DOP with Hardware-assisted Run-time Scope Enforcement
Widespread use of memory unsafe programming languages (e.g., C and C++)
leaves many systems vulnerable to memory corruption attacks. A variety of
defenses have been proposed to mitigate attacks that exploit memory errors to
hijack the control flow of the code at run-time, e.g., (fine-grained)
randomization or Control Flow Integrity. However, recent work on data-oriented
programming (DOP) demonstrated highly expressive (Turing-complete) attacks,
even in the presence of these state-of-the-art defenses. Although multiple
real-world DOP attacks have been demonstrated, no efficient defenses are yet
available. We propose run-time scope enforcement (RSE), a novel approach
designed to efficiently mitigate all currently known DOP attacks by enforcing
compile-time memory safety constraints (e.g., variable visibility rules) at
run-time. We present HardScope, a proof-of-concept implementation of
hardware-assisted RSE for the new RISC-V open instruction set architecture. We
discuss our systematic empirical evaluation of HardScope which demonstrates
that it can mitigate all currently known DOP attacks, and has a real-world
performance overhead of 3.2% in embedded benchmarks
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