An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes

Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 us, achieving a throughput of 27MbpsComment: 4 pages, 4 figures, 4 tables, Published in 27th International Conference on Field Programmable Logic and Applications (FPL), 201

Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes

In this work, we present hardware and software implementations of flexible polar systematic encoders and decoders. The proposed implementations operate on polar codes of any length less than a maximum and of any rate. We describe the low-complexity, highly parallel, and flexible systematic-encoding algorithm that we use and prove its correctness. Our hardware implementation results show that the overhead of adding code rate and length flexibility is little, and the impact on operation latency minor compared to code-specific versions. Finally, the flexible software encoder and decoder implementations are also shown to be able to maintain high throughput and low latency.Comment: Submitted to IEEE Transactions on Communications, 201

Fifth Generation (5G) New Radio (NR) Channel Codes Contenders Based on Field- Programmable Gate Arrays (FPGA): A Review Paper

ان الحاجة المتزايدة على الجودة، مثل السرعة العالية والتاخير المنخفض والتغطية الواسعة واستهلاك الطاقة والتكلفة والاتصالات الموثوقة في خدمات الهاتف المحمول والوسائط المتعددة ونقل البيانات تفرض استخدام المتطلبات التقنية المتقدمة في الجيل الخامس (5G) الإذاعة الجديدة (NR). واحدة من أهم الأجزاء في الطبقة المادية للجيل الجديد هي تقنية الترميز لتصحيح الأخطاء. هنالك ثلاثة اشكال مقترحة لتقنيات الترميز المخصصة لقنوات نقل البيانات وقنوات التحكم هي  الترميز التوربيني وفحص التكافؤ المنخفض الكثافة (LDPC) والرموز القطبية. يتم تقييم المنافسة بين هذه الانواع من حيث القدرة على تصحيح الأخطاء والتعقيد الحسابي والمرونة. التوازي والمرونة وسرعة المعالجة العالية لمصفوفة البوابة القابلة للبرمجة الميدانية (FPGA) تجعلها أفضل في النماذج الأولية وتنفيذ الرموز المختلفة. تقدم هذه الورقة دراسة استقصائية للبحوث الحالية التي تتعامل مع تصميم وحدة فك الترميز المستندة إلى FPGA المرتبطة برموز القناة المذكورة سابقًا.The increased demands for quality, like high throughput, low-latency, wide coverage, energy consumption, cost and reliable connections in mobile services, multimedia and data transmission impose the use of advance technical requirements for the next fifth-generation (5G) new radio (NR). One of the most crucial parts in the physical layer of the new generation is the error correction coding technique. Three schemes, namely; Turbo, low density parity check (LDPC), and polar codes are potentially ‎considered as the candidate codes for both data and control channels. The competition is evaluated in terms of error correction capability, computational complexity, and flexibility. The parallelism, flexibility and high processing speed of Field-Programmable Gate Array (FPGA) make it preferable in prototyping and implementation of different codes. This paper presents a survey on the current literatures that deals with FPGA-based decoder design associated with the previously mentioned channel codes