Modeling and Design of a Low-Level RF Control System for the Accumulator Ring at Spallation Neutron Source

Since its commissioning in 2006, Spallation Neutron Source (SNS) at Oak Ridge National Laboratory has greatly contributed to the field of neutron science, but some critical systems are reaching end-of-life. This obsolescence must be addressed for the accelerator to continue providing world-class research capabilities. One such system needing redesign is the low-level RF (LLRF) control system for the proton accumulator ring. While this system has performed acceptably for over a decade, it is sparsely documented and robust operational models are unavailable. To ensure the new design meets or exceeds current performance metrics, we analyzed the existing LLRF control system and designed a system-accurate controller model. This model included a state-space representation of the RF accelerator cavity dynamics. Both the controller and cavity models are combined to provide complete, functional simulation capabilities for the SNS accumulator ring LLRF control system. We then realized the modeled controller in an FPGA using VHDL cores which were subsequently used to successfully regulate the accumulator ring. The designed controller was functional at repetition rates up to 160 Hz while system specifications only require 60 Hz operation. The designed controller achieved 1 MW beam-on-target operation at 60 Hz repetition rate and a fundamental frequency of approximately 1 MHz

RF Power Amplifier Characterization for Predistortion Linearization

The purpose of this Major Qualifying Project was to develop and evaluate a digital baseband predistortion approach for radio frequency power amplifiers (RFPA). We also aimed to develop a hardware implementation of the system. The predistorter implements a look-up-table (LUT) to restore a baseband signal constellation and is simulated using actual RFPA characteristics. The testing includes the use of MATLAB, a Xilinx Spartan-3 FPGA as a pattern generator, a digital-to-analog converter (DAC), a modulator, an RFPA, and a demodulator

802.15.4 Low Intermediate Frequency Radio Receiver

This project involves the design, building, and testing of a low intermediate frequency 802.15.4 receiver that uses an FPGA to perform final demodulation to baseband

Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing

This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and was implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for data rates from 1 kbps to 8 kbps was implemented.DOI:http://dx.doi.org/10.11591/ijece.v4i3.556

S-Band QPSK Transmitter for Picosatellites

The small satellite field has become popular amongst academia, amateur satellite (AMSAT) community, and commercial businesses due to the miniaturization of components and smaller form factors. Specifically, the picosatellite structure has gained attraction for its size and affordability of launch fees. However, the size constraint makes it difficult to generate power and limits the transmit power for downlink. Therefore, efficient data modulation is key to providing high data downlink rates. Also, the typical VHF and UHF frequency spectrum used for satellites is getting congested. Hence, the higher frequency bands such as S-band and X-band are gaining attraction and offer higher data bandwidth. To address both issues, an architecture to implement QPSK modulation for S-band operation is proposed. The design is focused on low-power picosatellites and the implementation is targeted for academia and the AMSAT community

RHINO software-defined radio processing blocks

This MSc project focuses on the design and implementation of a library of parameterizable, modular and reusable Digital IP blocks designed around use in Software-Defined Radio (SDR) applications and compatibility with the RHINO platform. The RHINO platform has commonalities with the better known ROACH platform, but it is a significantly cut-down and lowercost alternative which has similarities in the interfacing and FPGA/Processor interconnects of ROACH. The purpose of the library and design framework presented in this work aims to alleviate some of the commercial, high cost and static structure concerns about IP cores provided by FPGA manufactures and third-party IP vendors. It will also work around the lack of parameters and bus compatibility issues often encountered when using the freely available open resources. The RHINO hardware platform will be used for running practical applications and testing of the blocks. The HDL library that is being constructed is targeted towards both novice and experienced low-level HDL developers who can download and use it for free, and it will provide them experience of using IP Cores that support open bus interfaces in order to exploit SoC design without commercial, parameter and bus compatibility limitations. The provided modules will be of particularly benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing blocks and associated RF receiver side configuration settings; all together these examples will help new developers establish effective ways to build their own SDR prototypes using RHINO

Framework of Real-Time Optical Nyquist-WDM Receiver using Matlab & Simulink

I investigate an optical Nyquist-WDM Bit Error Rate (BER) detection system. A transmitter and receiver system is simulated, using Matlab and Simulink, to form a working algorithm and to study the effects of the different processes of the data chain. The inherent lack of phase information in the N-WDM scheme presents unique challenges and requires a precise phase recovery system to accurately decode a message. Furthermore, resource constraints are applied by a cost-effective Field Programmable Gate Array (FPGA). To compensate for the speed, gate, and memory constraints of a budget FPGA, several techniques are employed to design the best possible receiver. I study the resource intensive operations and vary their resource utilization to discover the effect on the BER. To conclude, a full VHDL design is delineated, including peripheral initialization, input data sorting and storage, timing synchronization, state machine and control signal implementation, N-WDM demodulation, phase recovery, QAM decoding, and BER calculation

Design and Implementation of FPGA-Based Multi-Rate BPSK- QPSK Modem with Focus on Carrier Recovery and Time Synchronization

Regarding the high performance and reconfigurability of Field Programmable Gate Arrays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand, a wide variety of applications in communication systems benefits from Phase-Shift Keying (PSK) modulation. Therefore, with respect to practical constraints and limitations, design and implementation of a robust and efficient FPGA-based structure for PSK modulation is an attractive subject of study. In practice, there is an unavoidable oscillator frequency difference between the transmitter and receiver which poses many challenges for designers. This frequency offset makes carrier recovery and time synchronization as two essential functions of every receiver. The possible solution lies in the closed loop control techniques. In other words, without feedback-based controllers, acceptable performance in a digital radio link is unachievable. The Costas Loop is one of the most effective methods for carrier recovery and its advantage over other methods is that the error signal in the feedback loop is twice as accurate. The Gardner time synchronization method is also introduced as a closed loop clock and data recovery technique and, regarding to its performance, is a potential candidate to be implemented on FPGA-based platforms. The main body of this thesis work is related to the realization aspects of these methods on FPGA. The thesis spans from the design and implementation of a baseband digital transceiver to connecting it to a radio frequency device, forming a Binary/Quadrature PSK modem. The introduced platform is developed on National Instruments Universal Software Radio Peripheral (NI USRP) equipped with a Xilinx Kintex 7 FPGA. Many case studies were conducted to evaluate the performance of similar systems considering Signal to Noise Ratio (SNR). In this study, in addition to SNR, the effectiveness of the implemented transceiver has been evaluated based on its ability to deal with the carrier and symbol rate frequency offsets. The introduced platform shows promising results in its capability to resolve up to ±200 kHz carrier frequency offset and ±14 kHz symbol rate frequency offset (in 18 dB SNR). Furthermore, on the basis of the performed assessment, it is concluded that the introduced model is robust and potential to be applied in array-based or multi-channel networks

Implementação de Tx/Rx banda base para 802.11-2007 em FPGA

Mestrado em Engenharia Electrónica e TelecomunicaçõesO trabalho apresentado nesta dissertação teve como objectivo o desenvolvimento da camada física de um sistema de transmissão e recepção de sinais OFDM baseados no standard IEEE 802.11-2007. O sistema desenvolvido inclui geração de dados aleatórios, modulador QAM, inserção de pilotos e subportadora DC, IFFT com adição de Prefixo Cíclico, buffer de saída e o consequente oposto para o receptor. A dissertação encontra-se dividida em duas partes principais. Na primeira parte, o sistema foi projectado e simulado em Matlab através do ambiente Simulink com o auxílio dos blocos da Xilinx inseridos no seu software System Generator for DSP. Na segunda parte, foram adicionadas DACʼs ao transmissor e o próprio foi compilado para um bloco e testado no XtremeDSP Development Kit-IV da Nallatech que inclui uma Field-Programmable Gate Array. Todos os módulos foram desenhados usando os blocos do System Generator for DSP da Xilinx. O kit está conectado ao computador através de uma interface PCI. Os dados obtidos são exibidos em Matlab para a primeira parte e num osciloscópio para a segunda parte.It was the objective of this dissertation the development of the Physical Layer of an IEEE 802.11-2007 Transmitter-Receiver system for generating OFDM signals. The developed design includes random Data Generation, QAM Modulator, Pilots and DC subcarrier insertion, IFFT with Cyclic Prefix insertion, an Output Buffer and the subsequent opposite for its receiver. This dissertation was divided in two main segments. In the first segment, the system was designed and simulated in Matlab through the Simulink environment using Xilinxʼs System Generator for DSP blocks. In the second part, DACʼs where added to the transmitter in order to compile it into a single block and test it on Nallatechʼs XtremeDSP Development Kit-IV, which includes a Field-Programmable Gate Array. All modules were designed using Xilinxʼs System Generator for DSP blocks. The kit is connected to the computer through a PCI interface. Output data is displayed on the Matlab environment for part one and on an oscilloscope for part two

IR-UWB and OFDM-UWB Transceiver Nodes for Communication and Positioning Purposes

Résumé Ultra-wideband (UWB) a suscité l'intérêt de chercheurs et de l'industrie en raison de ses nombreux avantages tels que la faible probabilité d'interception et de la possibilité de combiner la communication des données de positionnement dans un seul système. Il existe plusieurs UWB couche physique (PHY) présentées initialement à la norme IEEE qui convergent en deux propositions principales: des porte-UWB ou Orthogonal Frequency-Division Multiplexing (OFDM-UWB), et à court d'impulsion porteuse à-UWB ou Impulse Radio-(IR-UWB). Une des plus grandes tâches difficiles pour les chercheurs est de nos jours la conception d'émetteurs-récepteurs UWB optimisés qui satisfont à des conditions rigoureuses, dont la simplicité caractéristiques large bande, à faible coût et de conception. Des études antérieures ont montré que les récepteurs à conversion directe basée sur Wave-radio interféromètre (WRI) circuits représentent un bon candidat pour les applications UWB. Circuits IRG ont plusieurs avantages tels que l'exploitation à large bande, à faible coût et la simplicité. Des travaux antérieurs sur l'IRG circuit, cependant, a enquêté sur le circuit de l'IRG sur la base du concept de porteuse unique signaux (par exemple, les signaux sinusoïdaux). L'objectif de ce projet est de fournir les résultats de conception, de simulation, de mise en oeuvre et le test d'un émetteur-récepteur WRI basé sur ce que peut être utilisé comme un noeud ou un pico-réseau dans un détecteur sans fil / réseau de données. Nous allons passer par les étapes de conception et de mise en oeuvre de propositions UWB deux: IR-UWB et OFDM-UWB. Pour la proposition porteuse à nous concentrer sur la conception et la mise en oeuvre de l'émetteur-récepteur en intégrant les opérations de transmission / réception dans un prototype unique, alors que pour la proposition des porte-nous concevoir et mettre en oeuvre l'émetteur-récepteur avec le circuit de l'IRG dans le récepteur seulement utilisé en tant que convertisseur abaisseur directe. Résultats expérimentaux, de simulation et d'analyse ont été obtenus et sont présentés dans cette thèse.----------Abstract Ultra-wideband (UWB) technology has attracted interest from both researchers and the industry due to its numerous advantages such as low probability of interception and the possibility of combining data communication with positioning in a single system. There are several different UWB physical layer (PHY) proposals originally submitted to IEEE which converged into two main proposals: carrier‐based UWB or Orthogonal-Frequency Division Multiplexing (OFDM‐UWB), and short‐pulse carrierless‐UWB or Impulse-Radio (IR-UWB). One of the biggest challenging tasks for researchers nowadays is the design of optimized UWB transceivers that would satisfy rigorous conditions, among which wideband characteristics, low-cost and design simplicity. Previous studies have shown that direct-conversion receivers based on Wave-Radio Interferometer (WRI) circuits represent a suitable candidate for UWB applications. WRI circuits have several advantages such as wideband operation, low cost, and simplicity. Previous works on WRI circuit, however, investigated the WRI circuit based on the concept of single-carrier signals (i.e., sinusoidal signals). The objective of this project is to provide the design, simulation, implementation and testing results of a WRI-based transceiver that can be utilized as a node or a piconet in a wireless sensor/data network. We will go through the design and implementation steps for both UWB proposals: IR-UWB and OFDM-UWB. For the carrierless proposal we will focus on designing and implementing the transceiver by integrating the transmitter/receiver operations in a single prototype, while for the carrier‐based proposal we will design and implement the transceiver with the WRI circuit in the receiver only utilized as a direct downconverter