Multi-standard programmable baseband modulator for next generation wireless communication

Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform the QPSK modulation schemes and as well as its other three commonly used variants to satisfy the requirement of several established 2G and 3G wireless communication standards. The proposed design has been shown to be capable of operating at a maximum data rate of 77 Mbps on Xilinx Virtex 2-Pro University field programmable gate array (FPGA) board. The pulse shaping root raised cosine (RRC) filter has been implemented using distributed arithmetic (DA) technique in the present work in order to reduce the computational complexity, and to achieve appropriate power reduction and enhanced throughput. The designed multiplier-less programmable 32-tap FIR-based RRC filter has been found to withstand a peak inter-symbol interference (ISI) distortion of -41 dB

Design and Implementation of FPGA-Based Multi-Rate BPSK- QPSK Modem with Focus on Carrier Recovery and Time Synchronization

Regarding the high performance and reconfigurability of Field Programmable Gate Arrays (FPGAs), many recent software defined radio (SDR) systems are currently being designed and developed on them. On the other hand, a wide variety of applications in communication systems benefits from Phase-Shift Keying (PSK) modulation. Therefore, with respect to practical constraints and limitations, design and implementation of a robust and efficient FPGA-based structure for PSK modulation is an attractive subject of study. In practice, there is an unavoidable oscillator frequency difference between the transmitter and receiver which poses many challenges for designers. This frequency offset makes carrier recovery and time synchronization as two essential functions of every receiver. The possible solution lies in the closed loop control techniques. In other words, without feedback-based controllers, acceptable performance in a digital radio link is unachievable. The Costas Loop is one of the most effective methods for carrier recovery and its advantage over other methods is that the error signal in the feedback loop is twice as accurate. The Gardner time synchronization method is also introduced as a closed loop clock and data recovery technique and, regarding to its performance, is a potential candidate to be implemented on FPGA-based platforms. The main body of this thesis work is related to the realization aspects of these methods on FPGA. The thesis spans from the design and implementation of a baseband digital transceiver to connecting it to a radio frequency device, forming a Binary/Quadrature PSK modem. The introduced platform is developed on National Instruments Universal Software Radio Peripheral (NI USRP) equipped with a Xilinx Kintex 7 FPGA. Many case studies were conducted to evaluate the performance of similar systems considering Signal to Noise Ratio (SNR). In this study, in addition to SNR, the effectiveness of the implemented transceiver has been evaluated based on its ability to deal with the carrier and symbol rate frequency offsets. The introduced platform shows promising results in its capability to resolve up to ±200 kHz carrier frequency offset and ±14 kHz symbol rate frequency offset (in 18 dB SNR). Furthermore, on the basis of the performed assessment, it is concluded that the introduced model is robust and potential to be applied in array-based or multi-channel networks

Single-Laser Multi-Terabit/s Systems

Optical communication systems carry the bulk of all data traffic worldwide. This book introduces multi-Terabit/s transmission systems and three key technologies for next generation networks. A software-defined multi-format transmitter, an optical comb source and an optical processing scheme for the fast Fourier transform for Tbit/s signals. Three world records demonstrate the potential: The first single laser 10 Tbit/s and 26 Tbit/s OFDM and the first 32.5 Tbit/s Nyquist WDM experiments

Single-Laser Multi-Terabit/s Systems

Optical communication systems carry the bulk of all data traffic worldwide. This book introduces multi-Terabit/s transmission systems and three key technologies for next generation networks. A software-defined multi-format transmitter, an optical comb source and an optical processing scheme for the fast Fourier transform for Tbit/s signals. Three world records demonstrate the potential: The first single laser 10 Tbit/s and 26 Tbit/s OFDM and the first 32.5 Tbit/s Nyquist WDM experiments

FPGA Implementation of the Front-End of a DOCSIS 3.0 Receiver

The introduction of cable television (CATV) in the 1940s and 1950s has significantly influenced communications technology. Originally supplying only one-way television programming, the CATV industry recognized the potential of two-way communications. Starting with the introduction of pay-per view services in the 1980s, two-way communications over CATV networks eventually expanded into supplying internet access services. The increased demand for CATV services, and thus the increased demand for CATV equipment, has led the CATV industry to develop interoperability standards. The primary standard now used by the CATV industry is the Data Over Cable Service Specification (DOCSIS). DOCSIS defines both the upstream (data towards the CATV provider) and downstream (data towards the CATV customer) transmission channels. This includes specifications for the modulators and demodulators used in these channels. The number of manufacturers of CATV modulators and demodulators has greatly increased over the last twenty years and continues to do so. As the number of competitive CATV equipment suppliers increases, these manufacturers must look to ways to remain competitive by reducing time-to-market and costs associated with equipment design, as well as allowing their designs to be flexible so that they may adapt to the improvements in DOCSIS. In the past, manufacturers have primarily used Application Specific Integrated Circuits (ASICs) to implement digital hardware designs for CATV equipment. ASICs have a very high initial setup cost and do not allow for system modifications without a complete redesign. Recently, Field Programmable Gate Array (FPGA) technology has been introduced that allows manufacturers to both modify their designed digital hardware structures without a complete physical hardware redesign, as well as providing a reduced initial setup cost. Although in the long term, ASICs provide a cheaper alternative to FPGAs when produced in quantity, FPGAs provide quicker time-to-market in new product development and allow changes to made after initial release. This ability to change designs after release and the quicker time-to-market has led manufacturers to adopt FPGAs in new products. A critical component in the upstream channel of a DOCSIS compliant system is the Quadrature Amplitude Modulated (QAM) receiver. The data received at the QAM receiver have undergone several impairments including additive noise, timing offset, and frequency and phase mismatches between the transmitted modulated signal and the signal received at the demodulator. It is the function of the front-end of the receiver to correct for these impairments. This thesis presents methods for, and an example of, the design and implementation of a DOCSIS compliant QAM receiver front-end that corrects for timing, phase and frequency impairments experienced in the upstream communication channel when additive noise is present. The circuits presented are designed and implemented to reduce hardware costs when using FPGA technology. In addition, the circuits designed do not use proprietary logic, which gives designers more flexibility when implementing their own demodulator front-end circuitry. The FPGA implementation presented in this thesis achieves an average MER of 54.3 dB in a no-noise channel and close to 31 dB MER in a 25 dBc AWGN channel. The overall design uses 65 dedicated 18-bit by 18-bit multipliers and 2,970 bytes of RAM to implement the digital front-end of the receiver

Fiber-on-Chip: Digital Emulation of Channel Impairments for Real-Time DSP Evaluation

We describe the Fiber-on-Chip (FoC) approach to verification of digital signal processing (DSP) circuits, where digital models of a fiber-optic communication system are implemented in the same hardware as the DSP under test. The approach can enable cost-effective long-term DSP evaluations without the need for complex optical-electronic testbeds with high-speed interfaces, shortening verification time and enabling deep bit-error rate evaluations. Our FoC system currently contains a digital model of a transmitter generating a pseudo-random bitstream and a digital model of a channel with additive white Gaussian noise, phase noise and polarization-mode dispersion. In addition, the FoC system contains digital features for real-time control of channel parameters, using low-speed communication interfaces, and for autonomous real-time analysis, which enable us to batch multiple unsupervised emulations on the same hardware. The FoC system can target both field-programmable gate arrays, for fast evaluation of fixed-point logic, and application-specific integrated circuits, for accurate power dissipation measurements

Real-time Digital Signal Processing for Software-defined Optical Transmitters and Receivers

A software-defined optical Tx is designed and demonstrated generating signals with various formats and pulse-shapes in real-time. Special pulse-shapes such as OFDM or Nyquist signaling were utilized resulting in a highly efficient usage of the available fiber channel bandwidth. This was achieved by parallel data processing with high-end FPGAs. Furthermore, highly efficient Rx algorithms for carrier and timing recovery as well as for polarization demultiplexing were developed and investigated

Simulating and Designing RF Transmitter for Small Satellites

This paper discusses the simulation and the design of an RF transmitter for small satellites operating in the commercial S- band (2.2 - 2.29 GHz) with a data rate of 8Mbps. In such systems, modelling frequency-dependent nonlinear characteristics of complex analog blocks and subsystems is critical for enabling efficient verification of mixed-signal system designs. In order to provide efficient and accurate simulation for the transmitter circuits, simple macromodels for weakly nonlinear mixer and power amplifier are used in the system simulation. Also, we introduce the noise in several circuits (frequency synthesizer, crystal oscillator, power amplifier, mixer,…) and we demonstrate their effect on the noise performance system. In the simulation we consider features of components and technologies commercially available

An investigation into the performance of a power-of-two coefficient transversal equalizer in a 34Mbit/s QPSK digital radio during frequency-selective fading conditions

Bibliography: leaves 82-91.Under certain atmospheric conditions, multipath propagation can occur. The interaction of radio waves arriving at a receiver, having travelled via paths of differing length, results in the phenomenon of frequency-selective fading. This phenomenon manifests as a notch in the received spectrum and causes a severe degradation in the performance of a digital radio system. As the total power in the received bandwidth may be unaffected, the Automatic Gain Control is not able to correct for this distortion, and so other methods are required. The dissertation commences with a summary of the phenomenon of multipath as this provides the context for the investigations which follow. The adaptive equalizer was developed to combat the distortion introduced by frequency-selective fading. It achieves this by applying an estimate of the inverse of the distorting channel's transfer function. The theory on adaptive equalizers has been well established, and a summary of this theory is presented in the form of Wiener Filter theory and the Wiener-Hopf equations. An adaptive equalizer located in a 34MBit/s QPSK digital radio is required to operate at very high speed, and its digital hardware implementation is not a trivial task. In order to reduce the cost and complexity, a compromise was proposed. If the tap weights of the equalizer could be represented by power-of-two binary numbers, the equalizer circuitry can be dramatically simplified. The aim of the dissertation was to investigate the performance of this simplified equalizer structure and to determine whether a power-of-two equalizer was a viable consideration