FPGA Implementation of a General Space Vector Approach on a 6-Leg Voltage Source Inverter

A general algorithm of a Space Vector approach is implemented on a 6-leg VSI controlling a PM synchronous machine with three independent phases. In this last case, the necessity of controlling the zero-sequence current motivates the choice of a special family of vectors, different of this one used in Pulse Width Modulation (PWM) intersective strategy and in common Space Vector PWM (SVPWM). To preserve the parallelism of the algorithm and fulfill the execution time constraints, the implementation is made on a Field Programmable Gate Array (FPGA). Comparisons with more classical 2-level and 3-level PWM are provided.Fui8 within the SOFRACI projec

A Survey: Space Vector PWM (SVPWM) in 3φ Voltage Source Inverter (VSI)

Since last decades, the pulse width modulation (PWM) techniques have been an intensive research subject. Also, different kinds of methodologies have been presented on inverter switching losses, inverter output current/ voltage total harmonic distortion (THD), inverter maximum output of DC bus voltage. The Sinusoidal PWM is generally used to control the inverter output voltage and it helps to maintains drive performance. The recent years have seen digital modulation mechanisms based on theory of space vector i.e. Space vector PWM (SVPWM). The SVPWM mechanism offers the enhanced amplitude modulation indexes (MI) than sinusoidal PWM along with the reduction in the harmonics of inverter output voltage and reduced communication losses. Currently, the digital control mechanisms have got more attention than the analog counterparts, as the performance and reliability of microprocessors has increased. Most of the SVPWM mechanisms are performed by using the analog or digital circuits like microcontrollers and DSPs. From the recent study, analysis gives that use of Field Programmable Gate Arrays (FPGA) can offer more efficient and faster solutions. This paper discusses the numerous existing research aspects of FPGA realization for voltage source inverter (VSI) along with the future line of research

Modified digital space vector pulse width modulation realization on low-cost FPGA platform with optimization for 3-phase voltage source inverter

The realization of power electronic applications on hardware is a challenging task. The digital control circuit strategies are used to overcome the analog control strategies by providing great flexibility with simple equipment and higher switching frequencies. In this manuscript, an area optimized, modified digital space vector (DSV) pulse width modulation is designed and realized on low-cost FPGA. The modified digital space vector pulse width modulation (DSVPWM) uses a phase-locked loop (PLL) to generate clocks using the digital clock manager (DCM). These DCM clocks are used in the DSVPWM module to synchronize the other sub-modules. The voltage generation unit generates the three-phase (3-Ф) voltages and is used in the alpha-beta generation and sector determination unit. The reference active vectors are made by the reference generation unit and used in switching time calculation. The PWM pulses are generated using switching time generation, and lastly, the dead time occurrence unit generates the final SVPWM gate pulses. The modified DSVPWM is synthesized and implemented on Spartan-3E FPGA. The modified DSVPWM utilizes 17% slices, works at 102.45 MHz, and consumes 0.070 W total power. The simulation results and the resource utilization of modified DSVPWM are represented in detail. The modified DSVPWM is compared with existing PWM approaches on different Spartan-series FPGAs with better chip area improvemen

Space Vector Modulation Techniques for Multilevel Converters – a survey

This paper presents a survey of most recent, simple and efficient Space Vector Modulation algorithms for multilevel converters. These algorithms avoid trigonometric and other complex operations, leading to more simple and cost efficient implementations. They can be applied to multilevel topologies and present freedom degrees that can be Exploited in order to optimize system parameters in the system like: capacitors voltages balancing or voltage/current ripples. Experimental results are presented to show the good performance of the algorithms

Implementation and verification of a hardware-basedcontroller for a three-phase induction motor on an FPGA

L’objectiu d’aquesta tesi és estudiar diverses tècniques de control motor per tal d’implementar i verificar un controlador basat en hardware per a un motor d’inducció trifàsic desenvolupat en llenguatge VHDL i funcionant en una FPGA Artix-7 (Xil-inx). Aquest controlador està basat en tècniques de variació de freqüència. Els mòduls que defineixen la descripció de hardware funcionen simultàniament entre ells, i permeten agilitzar el sistema, millorant el rendiment i la resposta del motor, en comparació amb un microcontrolador. Aquesta tesi està relacionada amb els sistemes digitals, l’electrònica de potència i els sistemes de control.Outgoin

Design, development and characterisation of a FPGA platform for multi-motor electric vehicle control

Two three-phase squirrel-cage induction motors are used as a propulsion system of an electric vehicle (EV). A simple XC3S1000 FPGA is used to simultaneously control both electric motors, with field oriented control and space vector modulation techniques. To electronically distribute the torque between the two electric motors, a simple, yet effective, strategy based on a uniform torque distribution has been implemented. Experimental results obtained with a multi-motor EV prototype demonstrate the proper operation of the proposed system

Simulink/Modelsim Co-Simulation and FPGA Realization of Speed Control IC for PMSM Drive

AbstractPMSM (Permanent Magnetic Synchronous Motor) has been increasingly used in many high performance application due to its advantages of high power density, high power factor and efficiency. The design and implementation of a fuzzy-control based speed control IC for PMSM from Simulink/Modelsim co-simulation to FPGA (Field Programmable Gate Array) realization is presented in this paper. Firstly, a SVPWM scheme, vector control method and fuzzy controller are derived and applied in the speed control IC of PMSM drive. Secondly, the Very-High-Speed IC Hardware Description Language (VHDL) is adopted to describe the behavior of the aforementioned control algorithms. To evaluate the effectiveness and correctness of the proposed speed control IC, a co-simulation work performed by Matlab/Simulink and Modelsim is firstly conducted. Then, an experimental system by FPGA chip, Nios processor and motor driving board is set up to further validate the performance of the proposed speed control IC. Finally, the results in simulation and in experiment will be compared and discussed

DESIGN OF FLOATING POINT PI CURRENT CONTROLLER FOR SPEED CONTROL OF IPMSM USING FPGA

The PI Controller can be considered as the essential part for efficient Speed Control of the Interior Permanent Magnet Synchronous Motor. In digital control, two platforms exist to implement this controller, namely DSP and FPGA. The FPGA is more preferred than the DSP due to the concurrent facility. To obtain the full facilities of the digital control and for high accuracy speed control of motors, floating point PI Controller should be used instead of the fixed point. The problem of the FPGA is that it is programmed using VHDL or Verilog which deals only with fixed-point representation. This paper shows a full design of floating-point PI Controller using Altera DE2i-150 platform and Altera Megafunctions. The results are proven using two simulation platforms ModelSim-Altera Starter Edition 15.0 and Matlab Simulink

Multilevel multiphase space vector PWM algorithm

In the last few years, interest in multiphase converter technology has increased due to the benefits of using more than three phases in drive applications. Besides, multilevel converter technology permits the achievement of high power ratings with voltage limited devices. Multilevel multiphase technology combines the benefits of both technologies, but new modulation techniques must be developed in order to take advantage of multilevel multiphase converters. In this paper, a novel space vector pulsewidth modulation (SVPWM) algorithm for multilevel multiphase voltage source converters is presented. This algorithm is the result of the two main contributions of this paper: the demonstration that a multilevel multiphase modulator can be realized from a two-level multiphase modulator, and the development of a new two-level multiphase SVPWM algorithm. The multiphase SVPWM algorithm presented in this paper can be applied to most multilevel topologies; it has low computational complexity and it is suitable for hardware implementations. Finally, the algorithm was implemented in a low-cost field-programmable gate array and it was tested in a laboratory with a real prototype using a five-level five-phase inverter.Ministerio de Educación y Ciencia | Ref. ENE2006-0293