Enhancement in iris recognition system using FPGA

The growth of using the iris recognition over the globe for identification and for verification and the problem that faces the iris recognition from noise like eyelash and eyelid. This paper focus on choosing the right pattern to collect the traits. The algorithm of this paper is searching and working on different rectangle iris template to spotting the ultimate traits that lies within rectangle iris templates. The Ridge Energy Direction (RED) is used as algorithm to spot the features that lies within the template. The overall iris system is design, implemented and tested on the Field Programmable gate Area (FPGA)

Band-Limited Phase-Only Correlation (Blpoc) Using Fpga For Finger Vein Recognition System

Nowadays, due to the high security and reliable of finger vein pattern, it had become one of the major interests in the biometric research. In the last few years, a number of finger vein recognition algorithms have been proposed. Most of the proposed methods were implemented in software-based on a general-purpose processor, which have limitations on the processing speed, size and power consumption. To overcome these limitations, this thesis presents an architecture for finger vein recognition system based on BLPOC matching method. The BLPOC is a phase-based matching method which have benefits of high accuracy and less affected by image shifted or brightness changed. It involves a high computation process, which is 2D-DFT, therefore, it is necessary to implement on a hardware device such as FPGA. It consists of two types of multiplexer blocks, one DFT block, one CORDIC block, seven types of memory blocks, one subtracter block, one divider block and one comparator block; and is implemented using Verilog HDL and verified using the Altera Cyclone III EP3C120F780 FPGA board. The proposed DFT block had contributed to reduce the area used by 97% of the previously proposed DFT block. A finger vein image database of 204 classes has been used to evaluate the performance of the proposed architecture. Results show that the proposed architecture can process a single matching of two finger vein images in 1.15 ms, which is about nine times faster than the softwarebased implementation, while the accuracy is similar with the software-based implementation. In conclusion, the finger vein recognition system based on BLPOC is successfully implemented on a FPGA board with better processing time as compared with the software-based implementation

Hardware-software co-design of an iris recognition algorithm

This paper describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose 32- bit microprocessor and several slave coprocessors that accelerate the most intensive calculations. The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared to a conventional software-based application. Experimental results show that with a clock speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480 pixels, which is just 20% of the total time needed by a software solution running on the same microprocessor embedded in the architecture.Peer ReviewedPreprin

Optimal load shedding for microgrids with unlimited DGs

Recent years, increasing trends on electrical supply demand, make us to search for the new alternative in supplying the electrical power. A study in micro grid system with embedded Distribution Generations (DGs) to the system is rapidly increasing. Micro grid system basically is design either operate in islanding mode or interconnect with the main grid system. In any condition, the system must have reliable power supply and operating at low transmission power loss. During the emergency state such as outages of power due to electrical or mechanical faults in the system, it is important for the system to shed any load in order to maintain the system stability and security. In order to reduce the transmission loss, it is very important to calculate best size of the DGs as well as to find the best positions in locating the DG itself.. Analytical Hierarchy Process (AHP) has been applied to find and calculate the load shedding priorities based on decision alternatives which have been made. The main objective of this project is to optimize the load shedding in the micro grid system with unlimited DG’s by applied optimization technique Gravitational Search Algorithm (GSA). The technique is used to optimize the placement and sizing of DGs, as well as to optimal the load shedding. Several load shedding schemes have been proposed and studied in this project such as load shedding with fixed priority index, without priority index and with dynamic priority index. The proposed technique was tested on the IEEE 69 Test Bus Distribution system

IRIS Feature Extraction and Classification using FPGA

An approach of singular value (SVD) of a (mxn) 2-D matrix has beenpopularly used by researchers for representing a 2-D image by a set of less than or equal to n values sequenced in descending order of which a subset of only first few values which are significant is treated as a set of features for that image. These features are further used for image recognition and classification. Though many papers as reviewed from literature have discussed about this implantation using software/MATLAB approach, rarely a paper appears on hardware implementation of SVD algorithm for image processing applications. This paper presents the details of a hardware architecture developed by us to implement SVD algorithm and then presents the results of implementation of this architecture in the Xilinx field programmable gate array Virtex5 to extract the features of an iris image. A comparison between the feature values extracted by MATLAB and those obtained by hardware simulation using Xilinx ISE tool indicates a very good match validating the hardware architecture. A hamming distance classifier using appropriate threshold values stored in ROM is used to classify the iris images.DOI:http://dx.doi.org/10.11591/ijece.v2i2.15

Online signature verification systems on a low-cost FPGA

This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision floating-point IEEE 754 format. The doubleprecision computations are replaced by simpler formats, without affecting the biometrics performance, in order to permit efficient implementations on low-cost FPGA families. The first approach is an embedded system based on MicroBlaze, a 32-bit soft-core microprocessor designed for Xilinx FPGAs, which can be configured by including a single-precision floating-point unit (FPU). The second implementation attaches a hardware accelerator to the embedded system to reduce the execution time on floating-point vectors. The last approach is a custom computing system, which is built from a large set of arithmetic circuits that replace the floating-point data with a more efficient representation based on fixed-point format. The latter system provides a very high runtime acceleration factor at the expense of using a large number of FPGA resources, a complex development cycle and no flexibility since it cannot be adapted to other biometric algorithms. By contrast, the first system provides just the opposite features, while the second approach is a mixed solution between both of them. The experimental results show that both the hardware accelerator and the custom computing system reduce the execution time by a factor ×7.6 and ×201 but increase the logic FPGA resources by a factor ×2.3 and ×5.2, respectively, in comparison with the MicroBlaze embedded system.This research was funded by Spanish MCIN/AEI/10.13039/501100011033, grant number PID2019-107274RB-I00.Peer ReviewedPostprint (published version

FPGA IMPLEMENTATION OF RED ALGORITHM FOR HIGH SPEED PUPIL ISOLATION

Iris recognition is an automated method of biometric identification that uses mathematical pattern-recognition techniques on video images of the irises of an individual’s eyes, whose complex random patterns are unique and can be seen from some distance. Modern iris recognition algorithms can be computationally intensive, yet are designed for traditional sequential processing elements, such as a personal computer. However, a parallel processing alternative using Field Programmable Gate Array offers an opportunity to speed up iris recognition. Within the means of this project, iris template generation with directional filtering, which is a computationally expensive, yet parallel portion of a modern iris recognition algorithm, is parallelized on an FPGA system. An algorithm that is both accurate and fast in a hardware design that is small and transportable are crucial to the implementation of this tool. As part of an ongoing effort to meet these criteria, this method improves a iris recognition algorithm, namely pupil isolation. A significant speed-up of pupil isolation by implementing this portion of the algorithm on a Field Programmable Gate Array

FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique

The real time fingerprint biometric system is implemented using FGPA. In this paper, we propose FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique with novel adaptive threshold for each person. The fingerprint images are considered from FVC2004 (DB3_A) and processed to resize fingerprint size to 256x256. The DWT is applied on fingerprint and considered only LL coefficients as features of fingerprint. The Adaptive Threshold value for each person is computed using Deviations between two successive samples of a person, Average Deviation, Standard Deviation and constant. The Adaptive Threshold for test image is computed using Deviations between test images and samples of database, Average Deviation, Standard Deviation and constant. If the Average Threshold of test image is less than Average Threshold of a person then it is considered as match else mismatched. It is observed that the success rate of identifying a person is high in the proposed method compared to existing techniques and also the device utilization in the proposed architecture is less compared to existing architecture