FPGA design and implementation of systolic array-based viterbi decoders

The Viterbi algorithm is known to provide an efficient method for the maximum likelihood decoding of convolutional codes. In this thesis, a design and FPGA implementation of a Viterbi decoder with a constraint length of 9 and code rate of 1/2 is presented. In this design, a novel systolic array architecture with time multiplexing, arithmetic pipelining and clock-to-data skews tolerance is developed. Further, by modifying this Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly-connected trellis decoding is proposed. Using the proposed adaptive algorithm, a design and FPGA implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and code rate of 1/2 is presented. The systolic array-based architecture used in this adaptive Viterbi decoder is a modified version of the architecture used for the non-adaptive Viterbi decoder in that the latter is modified to include the modules, which are needed for generating the survivor information and for eliminating the spurious toggles in the adaptive Viterbi decoding process

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance

Design a High Secure Adaptive VETERBI Encoder and Decoder Architectures

Mainly, Viterbi algorithm [V.A] is utilized in various applications such as cellular relay, satellite communication, and networks of wireless local area. This algorithm is mainly applied to the decoding conventional codes and also to automatic speech recognition and storage devices. In architecture of Viterbi algorithm, we are utilizing scheme of error detection which is based on the low complexity and low latency. The main benefit of this proposed system is that it gives reliable requirements and as well as performance degradation. We utilize three variants in the system which is recomputed with the encoded operands. Thus, this system is modified when we detect the both permanent faults [P.F] and transient faults which are mixed with signature based methods. Here, we are utilizing architecture of instrumented decoder for the motive of extensive error detection assessments. For the motive of bench mark we are improving the both application specific integrated circuit and field programmed gate array. Depend upon the reliability objectives and performance degradation tolerance, the proposed system is utilized

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs