39 research outputs found
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-Efficient Genome Analysis
Profile hidden Markov models (pHMMs) are widely employed in various
bioinformatics applications to identify similarities between biological
sequences, such as DNA or protein sequences. In pHMMs, sequences are
represented as graph structures. These probabilities are subsequently used to
compute the similarity score between a sequence and a pHMM graph. The
Baum-Welch algorithm, a prevalent and highly accurate method, utilizes these
probabilities to optimize and compute similarity scores. However, the
Baum-Welch algorithm is computationally intensive, and existing solutions offer
either software-only or hardware-only approaches with fixed pHMM designs. We
identify an urgent need for a flexible, high-performance, and energy-efficient
HW/SW co-design to address the major inefficiencies in the Baum-Welch algorithm
for pHMMs.
We introduce ApHMM, the first flexible acceleration framework designed to
significantly reduce both computational and energy overheads associated with
the Baum-Welch algorithm for pHMMs. ApHMM tackles the major inefficiencies in
the Baum-Welch algorithm by 1) designing flexible hardware to accommodate
various pHMM designs, 2) exploiting predictable data dependency patterns
through on-chip memory with memoization techniques, 3) rapidly filtering out
negligible computations using a hardware-based filter, and 4) minimizing
redundant computations.
ApHMM achieves substantial speedups of 15.55x - 260.03x, 1.83x - 5.34x, and
27.97x when compared to CPU, GPU, and FPGA implementations of the Baum-Welch
algorithm, respectively. ApHMM outperforms state-of-the-art CPU implementations
in three key bioinformatics applications: 1) error correction, 2) protein
family search, and 3) multiple sequence alignment, by 1.29x - 59.94x, 1.03x -
1.75x, and 1.03x - 1.95x, respectively, while improving their energy efficiency
by 64.24x - 115.46x, 1.75x, 1.96x.Comment: Accepted to ACM TAC
Acceleration of Profile-HMM Search for Protein Sequences in Reconfigurable Hardware - Master\u27s Thesis, May 2006
Profile Hidden Markov models are highly expressive representations of functional units, or motifs, conserved across protein sequences. Profile-HMM search is a powerful computational technique that is used to annotate new sequences by identifying occurrences of known motifs in them. With the exponential growth of protein databases, there is an increasing demand for acceleration of such techniques. We describe an accelerator for the Viterbi algorithm using a two-stage pipelined design in which the first stage is implemented in parallel reconfigurable hardware for greater speedup. To this end, we identify algorithmic modifications that expose a high level of parallelism and characterize their impact on the accuracy and performance relative to a standard software implementation. We develop a performance model to evaluate any accelerator design and propose two alternative architectures that recover the accuracy lost by a basic architecture. We compare the performance of the two architectures to show that speedups of up to 3 orders of magnitude may be achieved. We also investigate the use of the Forward algorithm in the first pipeline stage of the accelerator using floating-point arithmetic and report its accuracy and performance
Parallelization of dynamic programming recurrences in computational biology
The rapid growth of biosequence databases over the last decade has led to a performance bottleneck in the applications analyzing them. In particular, over the last five years DNA sequencing capacity of next-generation sequencers has been doubling every six months as costs have plummeted. The data produced by these sequencers is overwhelming traditional compute systems. We believe that in the future compute performance, not sequencing, will become the bottleneck in advancing genome science. In this work, we investigate novel computing platforms to accelerate dynamic programming algorithms, which are popular in bioinformatics workloads. We study algorithm-specific hardware architectures that exploit fine-grained parallelism in dynamic programming kernels using field-programmable gate arrays: FPGAs). We advocate a high-level synthesis approach, using the recurrence equation abstraction to represent dynamic programming and polyhedral analysis to exploit parallelism. We suggest a novel technique within the polyhedral model to optimize for throughput by pipelining independent computations on an array. This design technique improves on the state of the art, which builds latency-optimal arrays. We also suggest a method to dynamically switch between a family of designs using FPGA reconfiguration to achieve a significant performance boost. We have used polyhedral methods to parallelize the Nussinov RNA folding algorithm to build a family of accelerators that can trade resources for parallelism and are between 15-130x faster than a modern dual core CPU implementation. A Zuker RNA folding accelerator we built on a single workstation with four Xilinx Virtex 4 FPGAs outperforms 198 3 GHz Intel Core 2 Duo processors. Furthermore, our design running on a single FPGA is an order of magnitude faster than competing implementations on similar-generation FPGAs and graphics processors. Our work is a step toward the goal of automated synthesis of hardware accelerators for dynamic programming algorithms
Hardware Accelerated DNA Sequencing
DNA sequencing technology is quickly evolving. The latest developments ex-
ploit nanopore sensing and microelectronics to realize real-time, hand-held devices.
A critical limitation in these portable sequencing machines is the requirement of
powerful data processing consoles, a need incompatible with portability and wide
deployment. This thesis proposes a rst step towards addressing this problem, the
construction of specialized computing modules { hardware accelerators { that can
execute the required computations in real-time, within a small footprint, and at a
fraction of the power needed by conventional computers. Such a hardware accel-
erator, in FPGA form, is introduced and optimized specically for the basecalling
function of the DNA sequencing pipeline. Key basecalling computations are identi-
ed and ported to custom FPGA hardware. Remaining basecalling operations are
maintained in a traditional CPU which maintains constant communications with
its FPGA accelerator over the PCIe bus. Measured results demonstrated a 137X
basecalling speed improvement over CPU-only methods while consuming 17X less
power than a CPU-only method
Characterizing and Accelerating Bioinformatics Workloads on Modern Microarchitectures
Bioinformatics, the use of computer techniques to analyze biological data, has been a particularly active research field in the last two decades. Advances in this field have contributed to the collection of enormous amounts of data, and the sheer amount of available data has started to overtake the processing capability possible with current computer systems. Clearly, computer architects need to have a better understanding of how bioinformatics applications work and what kind of architectural techniques could be used to accelerate these important scientific workloads on future processors. In this dissertation, we develop a bioinformatic benchmark suite and provide a detailed characterization of these applications in common use today from a computer architect's point of view. We analyze a wide range of detailed execution characteristics including instruction mix, IPC measurements, L1 and L2 cache misses on a real architecture; and proceed to analyze the workloads' memory access characteristics. We then concentrate on accelerating a particularly computationally intensive bioinformatics workload on the novel Cell Broadband Engine multiprocessor architecture. The HMMER workload is used for protein profile searching using hidden Markov models, and most of its execution time is spent running the Viterbi algorithm. We parallelize and partition the HMMER application to implement it on the Cell Broadband Engine. In order to run the Viterbi algorithm on the 256KB local stores of the Cell BE synergistic processing units (SPEs), we present a method to develop a fast SIMD implementation of the Viterbi algorithm that reduces the storage requirements significantly. Our HMMER implementation for the Cell BE architecture, Cell-HMMER, exploits the multiple levels of parallelism inherent in this application, and can run protein profile searches up to 27.98 times faster than a modern dual-core x86 microprocessor
Design of hardware architectures for HMM–based signal processing systems with applications to advanced human-machine interfaces
In questa tesi viene proposto un nuovo approccio per lo sviluppo di interfacce uomo–macchina. In particolare si
tratta il caso di sistemi di pattern recognition che fanno uso di Hidden Markov Models per la classificazione.
Il progetto di ricerca è partito dall’ideazione di nuove tecniche per la realizzazione di sistemi di riconoscimento
vocale per parlato spontaneo. Gli HMM sono stati scelti come lo strumento algoritmico di base per la realizzazione
del sistema. Dopo una fase di studio preliminare gli obiettivi sono stati estesi alla realizzazione di una architettura
hardware in grado di fornire uno strumento riconfigurabile che possa essere utilizzato non solo per il riconoscimento
vocale, ma in qualsiasi tipo di classificatore basato su HMM.
Il lavoro si concentra quindi sullo sviluppo di architetture hardware dedicate, ma nuovi risultati sono stati ottenuti
anche a livello di applicazione per quanto riguarda la classificazione di segnali elettroencefalografici attraverso
gli HMM.
Innanzitutto state sviluppata una architettura a livello di sistema applicabile a qualsiasi sistema di pattern
recognition che faccia usi di HMM. L’architettura stata concepita in modo tale da essere utilizzabile come un
sistema stand–alone. Definita l’architettura, un processore hardware per HMM, completamente riconfigurabile,
stato decritto in linguaggio VHDL e simulato con successo. Un array parallelo di questi processori costituisce di
fatto il nucleo di processamento dell’architettura sviluppata.
Sulla base del progetto in VHDL, due piattaforme di prototipaggio rapido basate su FPGA sono state selezionate
per dei test di implementazione. Diverse configurazioni costituite da array paralleli di processori HMM sono state
implementate su FPGA. Le soluzioni che offrivano un miglior compromesso tra prestazioni e quantitĂ di risorse
hardware utilizzate sono state selezionate per ulteriori analisi.
Un sistema software per il pattern recognition basato su HMM stato scelto come sistema di riferimento per
verificare la corretta funzionalitĂ delle architetture implementate. Diversi test sono stati progettati per validare che
il funzionamento del sistema corrispondesse alle specifiche iniziali. Le versioni implementate del sistema sono state
confrontate con il software di riferimento sulla base dei risultati forniti dai test. Dal confronto è stato possibile
appurare che le architetture sviluppate hanno un comportamento corrispondente a quello richiesto.
Infine le implementazioni dell’array parallelo di processori HMM `e sono state applicate a due applicazioni reali:
un riconoscitore vocale, ed un classificatore per interfacce basate su segnali elettroencefalografici. In entrambi i
casi l’architettura si è dimostrata in grado di gestire l’applicazione senza alcun problema. L’uso del processamento
hardware per il riconoscimento vocale apre di fatto la strada a nuovi sviluppi nel campo grazie al notevole incremento
di prestazioni ottenibili in termini di tempo di esecuzione. L’applicazione al processamento dell’EEG, invece,
introduce di fatto un approccio completamente nuovo alla classificazione di questo tipo di segnali, e mostra come in
futuro potrebbe essere possibile lo sviluppo di interfacce basate sulla classificazione dei segnali generati dal pensiero
spontaneo.
I possibili sviluppi del lavoro iniziato con questa tesi sono molteplici. Una direzione possibile è quella dell’implementazione
completa dell’architettura proposta come un sistema stand–alone riconfigurabile per l’accelerazione
di sistemi per pattern recognition di qualsiasi natura purchè basati su HMM. Le potenzialità di tale sistema renderebbero
possibile la realizzazione di classificatiori in tempo reale con un alto grado di complessitĂ , e quindi allo
sviluppo di interfacce realmente multimodali, con una vasta gamma di applicazioni, dai sistemi di per lo spazio a
quelli di supporto per persone disabili.In this thesis a new approach is described for the development of human–computer interfaces. In particular
the case of pattern recognition systems based on Hidden Markov Models have been taken into account.
The research started from he development of techniques for the realization of natural language speech
recognition systems. The Hidden Markov Model (HMM) was chosen as the main algorithmic tool to be
used to build the system. After the early work the goal was extended to the development of an hardware
architecture that provided a reconfigurable tool to be used in any pattern recognition task, and not only in
speech recognition.
The whole work is thus focused on the development of dedicated hardware architectures, but also some
new results have been obtained on the classification of electroencephalographic signals through the use of
HMMs.
Firstly a system–level architecture has been developed to be used in HMM based pattern recognition
systems. The architecture has been conceived in order to be able to work as a stand–alone system. Then a
VHDL description has been made of a flexible and completely reconfigurable hardware HMM processor and
the design was successfully simulated. A parallel array of these processors is actually the core processing
block of the developed architecture.
Then two suitable FPGA based, fast prototyping platforms have been identified to be the targets for
the implementation tests. Different configurations of parallel HMM processor arrays have been set up and
mapped on the target FPGAs. Some solutions have been selected to be the best in terms of balance between
performance and resources utilization.
Furthermore a software HMM based pattern recognition system has been chosen to be the reference system
for the functionality of the implemented subsystems. A set of tests have been developed with the aim to test
the correct functionality of the hardware. The implemented system was compared to the reference system
on the basis of the tests’ results, and it was found that the behavior was the one expected and the required
functionality was correctly achieved.
Finally the implementation of the parallel HMM array was tested through its application to two real–world
applications: a speech recognition task and a brain–computer interface task. In both cases the architecture
showed to be functionally suitable and powerful enough to handle the task without problems. The application
of the hardware processing to speech recognition opens new perspectives in the design of this kind of systems
because of the dramatic increment in performance. The application to brain–computer interface is really
interesting because of a new approach in the classification of EEG that shows how could be possible a future
development of interfaces based on the classification of spontaneous thought.
The possible evolution directions of the work started with this thesis are many. Effort could be spent of
the implementation of the developed architecture as a stand–alone reconfigurable system suitable for any kind
of HMM–based pattern recognition task. The potential performance of such a system could open the way
to extremely complex real–time pattern recognition systems, and thus to the realization of truly multimodal
interfaces, with a variety of applications, from space to aid systems for the impaired
Bioinformatics
This book is divided into different research areas relevant in Bioinformatics such as biological networks, next generation sequencing, high performance computing, molecular modeling, structural bioinformatics, molecular modeling and intelligent data analysis. Each book section introduces the basic concepts and then explains its application to problems of great relevance, so both novice and expert readers can benefit from the information and research works presented here