ASIC-in-the-loop methodology for verification of piecewise affine controllers

This paper exposes a hardware-in-the-loop metho- dology to verify the performance of a programmable and confi- gurable application specific integrated circuit (ASIC) that imple- ments piecewise affine (PWA) controllers. The ASIC inserted into a printed circuit board (PCB) is connected to a logic analyzer that generates the input patterns to the ASIC (in particular, the values to program the memories, configuration parameters, and values of the input signals). The output provided by the ASIC is also taken by the logic analyzer. A Matlab program controls the logic analyzer to verify the PWA controller implemented by the ASIC in open-loop as well as in closed-loop configurations.Comunidad Europea FP7-INFSO-ICT-248858Gobierno Español TEC2011-24319Junta de Andalucía P08-TIC-0367

High-Speed and Low-Cost Implementation of Explicit Model Predictive Controllers

This paper presents a new form of piecewise-affine (PWA) solution, referred to as PWA hierarchical (PWAH), to approximate the explicit model predictive control (MPC) law, achieving a very rapid control response with the use of very few computational and memory resources. This is possible because PWAH controllers consist of single-input single-output PWA modules connected in cascade so that the parameters needed to define them increase linearly instead of exponentially with the input dimension of the control problem. PWAH controllers are not universal approximators but several explicit MPC controllers can be efficiently approximated by them. A methodology to design PWAH controllers is presented and validated with application examples already solved by MPC approaches. The designed PWAH controllers implemented in field-programmable gate arrays provide the highest control speed using the fewest resources compared with the other digital implementations reported in the literature.Ministerio de Economía, Industria y Competitividad TEC2014-57971-

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture.Peer reviewe

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

This paper presents a small, fast, low-power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for very-large-scale integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for field-programmable gate arrays and application-specific integrated circuits are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost dc-dc converter) are included to illustrate the performance of the VLSI solution obtained with the proposed lattice-based architecture

VLSI Design of Trusted Virtual Sensors

This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time)Ministerio de Economía, Industria y Competitividad TEC2014-57971-RConsejo Superior de Investigaciones Científicas 201750E01

FPGA Implementations of Piecewise Affine Functions Based on Multi-Resolution Hyperrectangular Partitions

In this paper we propose a digital architecture suited for fast, low-power and small-size electronic implementation of PieceWise Affine (PWA) functions defined over n-dimensional domains partitioned into multi-resolution hyperrectangles. The point location problem, which requires most of the computational effort, is solved through an orthogonal search tree, which is easily and efficiently implementable. In the case of domains partitioned into single-resolution hyperrectangles, a simpler and even faster architecture is proposed. After introducing the new architectures, their key features are discussed and compared to previous architectures implementing PWA functions with domains partitioned into different types of polytopes. Case studies concerning the FPGA implementation of so-called explicit Model Predictive Control (MPC) laws for constrained linear systems are used as benchmarks to compare the different architectures