59 research outputs found

    Investigation and Implementation of Dicode Pulse Position Modulation Over Indoor Visible Light Communication System

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    A visible light communication (VLC) system with green technology is available and enables users to use white LEDs for illumination as well as for high data rate transmission over wireless optical links. In addition, LEDs have advantages of low power consumption, high speed with power efficiency and low cost. Therefore, a great deal of research is considered for indoor VLC, as it offers huge bandwidth whilst using a significant modulation technique. This thesis is concerned with the investigation and implementation of the dicode pulse position modulation (DiPPM) scheme over a VLC link using white LED sources. Novel work is carried out for applying DiPPM over a VLC channel theoretically and experimentally including a comparison with digital PPM (DPPM) in order to examine the system performance. Moreover, a proposal of variable DiPPM (VDiPPM) is presented in this thesis for dimming control. The indoor VLC channel characteristics have been investigated for two propagation prototypes. Two models have been proposed and developed with DiPPM and DPPM being applied over the VLC channel. A computer simulation for the proposed models for both DiPPM and DPPM systems is performed in order to analyse the receiver sensitivity with the effect of intersymbol interference (ISI). Both systems are operating at 100 Mbps and 1 Gbps for a BER of 10-9. An improvement in sensitivity being achieved by the DiPPM compared to the DPPM VLC system. The system performance has been carried out by Mathcad software. The predicted DiPPM receiver sensitivity outperforms DPPM receiver at by -5.55 dBm and -8.24 dBm, at 1 Gbps data rate, and by -5.53 dBm and -8.22 dBm, at 100 Mbps, without and with guard intervals, respectively. In both cases the optical receiver sensitivity is increased when the ISI is ignored. These results based on the received optical power required by each modulation scheme. Further work has been done in mathematical evaluation carried out to calculate the optical receiver sensitivity to verify the comparison between the two systems. The original numerical results show that DiPPM VLC system provides a better sensitivity than a DPPM VLC system at a selected BER of 10-9 when referred to the same preamplifier at wavelength of 650 nm and based on the equivalent input noise current generated by the optical front end receiver. The results show that the predicted sensitivity for DPPM is greater than that of DPPM by about 1 dBm when both systems operating at 100 Mbps and 1 Gbps. Also, it is show that the receiver sensitivity is increased when the ISI is limited. Experimentally, a complete indoor VLC system has been designed and implemented using Quartus II 11.1 software for generating VHDL codes and using FPGA development board (Cyclone IV GX) as main interface real-time transmission unit in this system. The white LEDs chip based transmitter and optical receiver have been constructed and tested. The measurements are performed by using LED white light as an optical transmitter faced to photodiode optical receiver on desk. Due to the LED bandwidth limitation the achieved operating data rate, using high speed LED driver, is 5.5 Mbps at BER of 10-7. The original results for the measurements determined that the average photodiode current produced by using DiPPM and DPPM optical receivers are 8.50 μA and 10.22 μA, respectively. And this in turn indicates that the DiPPM receiver can give a better sensitivity of -17.24 dBm while compared to the DPPM receiver which gives is -16.44 dBm. The original practical results proved the simulation and theoretical results where higher performance is achieved when a DiPPM scheme is used compared to DPPM scheme over an indoor VLC system

    Highly-configurable FPGA-based platform for wireless network research

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-164).Over the past few years, researchers have developed many cross-layer wireless protocols to improve the performance of wireless networks. Experimental evaluations of these protocols require both high-speed simulations and real-time on-air experimentations. Unfortunately, radios implemented in pure software are usually inadequate for either because they are typically two to three orders of magnitude slower than commodity hardware. FPGA-based platforms provide much better speeds but are quite difficult to modify because of the way high-speed designs are typically implemented by trading modularity for performance. Experimenting with cross-layer protocols requires a flexible way to convey information beyond the data itself from lower to higher layers, and a way for higher layers to configure lower layers dynamically and within some latency bounds. One also needs to be able to modify a layer's processing pipeline without triggering a cascade of changes. In this thesis, we discuss an alternative approach to implement a high-performance yet configurable radio design on an FPGA platform that satisfies these requirements. We propose that all modules in the design must possess two important design properties, namely latency-insensitivity and datadriven control, which facilitate modular refinements. We have developed Airblue, an FPGA-based radio, that has all these properties and runs at speeds comparable to commodity hardware. Our baseline design is 802.11g compliant and is able to achieve reliable communication for bit rates up to 24 Mbps. We show in the thesis that we can implement SoftRate, a cross-layer rate adaptation protocol, by modifying only 5.6% of the source code (967 lines). We also show that our modular design approach allows us to abstract the details of the FPGA platform from the main design, thus making the design portable across multiple FPGA platforms. By taking advantage of this virtualization capability, we were able to turn Airblue into a high-speed hardware software co-simulator with simulation speed beyond 20 Mbps.by Man Cheuk Ng.Ph.D
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