Configurable 3D-integrated focal-plane sensor-processor array architecture

A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources

Prognostic Reasoner based adaptive power management system for a more electric aircraft

This research work presents a novel approach that addresses the concept of an adaptive power management system design and development framed in the Prognostics and Health Monitoring(PHM) perspective of an Electrical power Generation and distribution system(EPGS).PHM algorithms were developed to detect the health status of EPGS components which can accurately predict the failures and also able to calculate the Remaining Useful Life(RUL), and in many cases reconfigure for the identified system and subsystem faults. By introducing these approach on Electrical power Management system controller, we are gaining a few minutes lead time to failures with an accurate prediction horizon on critical systems and subsystems components that may introduce catastrophic secondary damages including loss of aircraft. The warning time on critical components and related system reconfiguration must permits safe return to landing as the minimum criteria and would enhance safety. A distributed architecture has been developed for the dynamic power management for electrical distribution system by which all the electrically supplied loads can be effectively controlled.A hybrid mathematical model based on the Direct-Quadrature (d-q) axis transformation of the generator have been formulated for studying various structural and parametric faults. The different failure modes were generated by injecting faults into the electrical power system using a fault injection mechanism. The data captured during these studies have been recorded to form a “Failure Database” for electrical system. A hardware in loop experimental study were carried out to validate the power management algorithm with FPGA-DSP controller. In order to meet the reliability requirements a Tri-redundant electrical power management system based on DSP and FPGA has been develope

Optimization of star research algorithm for esmo star tracker

This paper explains in detail the design and the development of a software research star algorithm, embedded on a star tracker, by the ISAE/SUPAERO team. This research algorithm is inspired by musical techniques. This work will be carried out as part of the ESMO (European Student Moon Orbiter) project by different teams of students and professors from ISAE/SUPAERO (Institut Supe ́rieur de l’Ae ́ronautique et de l’Espace). Till today, the system engineering studies have been completed and the work that will be presented will concern the algorithmic and the embedded software development. The physical architecture of the sensor relies on APS 750 developed by the CIMI laboratory of ISAE/SUPAERO. First, a star research algorithm based on the image acquired in lost-in-space mode (one of the star tracker opera- tional modes) will be presented; it is inspired by techniques of musical recognition with the help of the correlation of digital signature (hash) with those stored in databases. The musical recognition principle is based on finger- printing, i.e. the extraction of points of interest in the studied signal. In the musical context, the signal spectrogram is used to identify these points. Applying this technique in image processing domain requires an equivalent tool to spectrogram. Those points of interest create a hash and are used to efficiently search within the database pre- viously sorted in order to be compared. The main goals of this research algorithm are to minimise the number of steps in the computations in order to deliver information at a higher frequency and to increase the computation robustness against the different possible disturbances

StrathSat-R : Deploying inflatable CubeSat structures in micro gravity

This paper presents the concepts, objectives and design of a student-led sounding rocket experiment which shall test novel inflatable devices in space conditions. This experiment is envisaged as the first step towards developing a CubeSat programme at the University of Strathclyde, which can exploit the novel concepts developed and the technical skills gained. The experiment itself aims to test novel, student developed, inflatable space structures in micro gravity and reduced pressure conditions. It consists of three distinct sections, the ejection housing on the rocket and the two ejectable modules that are based on CubeSat architecture. Shortly before reaching apogee, the two modules are ejected from the rocket and will deploy their own inflating structure during free flight. After landing, the ejectable modules recovery will rely upon a GPS position relayed to the team from the module by Globalstar transmission and a RF beacon for tracking with the recovery helicopter. The two modules carry two different structures resulting in distinct mission objectives: The aim of FRODO is to deploy an experimental passive de-orbiting system for high altitude spacecraft which will in the future utilise solar radiation pressure for orbit removal. The aim of SAM is to serve as a technology demonstrator for the residual air deployment method of a smart bio-inspired space structure. This paper contains details about the science objectives of the mission and how they will be achieved, its experimental design and the management of the student-led project

Multistage Switching Architectures for Software Routers

Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of single software routers, ii) scale router size, iii) distribute packet manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, largesize,scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is under wa

Vector coprocessor sharing techniques for multicores: performance and energy gains

Vector Processors (VPs) created the breakthroughs needed for the emergence of computational science many years ago. All commercial computing architectures on the market today contain some form of vector or SIMD processing. Many high-performance and embedded applications, often dealing with streams of data, cannot efficiently utilize dedicated vector processors for various reasons: limited percentage of sustained vector code due to substantial flow control; inherent small parallelism or the frequent involvement of operating system tasks; varying vector length across applications or within a single application; data dependencies within short sequences of instructions, a problem further exacerbated without loop unrolling or other compiler optimization techniques. Additionally, existing rigid SIMD architectures cannot tolerate efficiently dynamic application environments with many cores that may require the runtime adjustment of assigned vector resources in order to operate at desired energy/performance levels. To simultaneously alleviate these drawbacks of rigid lane-based VP architectures, while also releasing on-chip real estate for other important design choices, the first part of this research proposes three architectural contexts for the implementation of a shared vector coprocessor in multicore processors. Sharing an expensive resource among multiple cores increases the efficiency of the functional units and the overall system throughput. The second part of the dissertation regards the evaluation and characterization of the three proposed shared vector architectures from the performance and power perspectives on an FPGA (Field-Programmable Gate Array) prototype. The third part of this work introduces performance and power estimation models based on observations deduced from the experimental results. The results show the opportunity to adaptively adjust the number of vector lanes assigned to individual cores or processing threads in order to minimize various energy-performance metrics on modern vector- capable multicore processors that run applications with dynamic workloads. Therefore, the fourth part of this research focuses on the development of a fine-to-coarse grain power management technique and a relevant adaptive hardware/software infrastructure which dynamically adjusts the assigned VP resources (number of vector lanes) in order to minimize the energy consumption for applications with dynamic workloads. In order to remove the inherent limitations imposed by FPGA technologies, the fifth part of this work consists of implementing an ASIC (Application Specific Integrated Circuit) version of the shared VP towards precise performance-energy studies involving high- performance vector processing in multicore environments

Ultra Low Power FPGA-Based Architecture for Wake-up Radio in Wireless Sensor Networks

In this paper the capabilities of ultra low power FPGAs to implement Wake-up Radios (WuR) for ultra low energy Wireless Sensor Networks (WSNs) are analyzed. The main goal is to evaluate the utilization of very low power configurable devices to take advantage of their speed, flexibility and low power consumption instead of the more common approaches based on ASICs or microcontrollers. In this context, energy efficiency is a key aspect, considering that usually the instant power consumption is considered a figure of merit, more than the total energy consumed by the application