Fault-tolerant multichannel demultiplexer subsystems

Fault tolerance in future processing and switching communication satellites is addressed by showing new methods for detecting hardware failures in the first major subsystem, the multichannel demultiplexer. An efficient method for demultiplexing frequency slotted channels uses multirate filter banks which contain fast Fourier transform processing. All numerical processing is performed at a lower rate commensurate with the small bandwidth of each bandbase channel. The integrity of the demultiplexing operations is protected by using real number convolutional codes to compute comparable parity values which detect errors at the data sample level. High rate, systematic convolutional codes produce parity values at a much reduced rate, and protection is achieved by generating parity values in two ways and comparing them. Parity values corresponding to each output channel are generated in parallel by a subsystem, operating even slower and in parallel with the demultiplexer that is virtually identical to the original structure. These parity calculations may be time shared with the same processing resources because they are so similar

Blind equalization based on spatial and temporal diversity in block coded modulations

Linear block codes can be applied in spatial and/or temporal diversity receivers in order to develop high performance schemes for blind equalization in mobile communications. The proposed technique uses the structure of the encoded transmitted information (with redundancy) to achieve equalization schemes based on a deterministic criterion. Simulations show that the proposed technique is more efficient than other schemes that follow similar equalizer structures. The result is an algorithm that provides the design of blind channel equalizers in low EbNo scenarios.Peer ReviewedPostprint (published version

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient

An Efficiency Study on Fault Tolerent Fir Filters

In this Digital World, Digital filters are the boom for modern digital communications in which Fir filters play a vital role. But the reliability of these filters is still a paradox. Nowadays electronic devices with multiple numbers of filters are used in various fields. Hence the performance and reliability of the filters must be improved. A number of techniques have been introduced to detect and correct errors that occur in those filter circuits. In this paper, the use of hamming code error correction technique on 4 tap fir filters are studied in order to obtain optimized and efficient reliability

Investigation of the use of infinite impulse response filters to construct linear block codes

A dissertation submitted in ful lment of the requirements for the degree of Masters in Science in the Information Engineering School of Electrical and Information Engineering August 2016The work presented extends and contributes to research in error-control coding and information theory. The work focuses on the construction of block codes using an IIR lter structure. Although previous works in this area uses FIR lter structures for error-detection, it was inherently used in conjunction with other error-control codes, there has not been an investigation into using IIR lter structures to create codewords, let alone to justify its validity. In the research presented, linear block codes are created using IIR lters, and the error-correcting capabilities are investigated. The construction of short codes that achieve the Griesmer bound are shown. The potential to construct long codes are discussed and how the construction is constrained due to high computational complexity is shown. The G-matrices for these codes are also obtained from a computer search, which is shown to not have a Quasi-Cyclic structure, and these codewords have been tested to show that they are not cyclic. Further analysis has shown that IIR lter structures implements truncated cyclic codes, which are shown to be implementable using an FIR lter. The research also shows that the codewords created from IIR lter structures are valid by decoding using an existing iterative soft-decision decoder. This represents a unique and valuable contribution to the eld of error-control coding and information theory.MT201

Power and Bandwidth Efficient Coded Modulation for Linear Gaussian Channels

A scheme for power- and bandwidth-efficient communication on the linear Gaussian channel is proposed. A scenario is assumed in which the channel is stationary in time and the channel characteristics are known at the transmitter. Using interleaving, the linear Gaussian channel with its intersymbol interference is decomposed into a set of memoryless subchannels. Each subchannel is further decomposed into parallel binary memoryless channels, to enable the use of binary codes. Code bits from these parallel binary channels are mapped to higher-order near-Gaussian distributed constellation symbols. At the receiver, the code bits are detected and decoded in a multistage fashion. The scheme is demonstrated on a simple instance of the linear Gaussian channel. Simulations show that the scheme achieves reliable communication at 1.2 dB away from the Shannon capacity using a moderate number of subchannels