Optimisation des jonctions de dispositifs (FDSOI, TriGate) fabriqués à faible température pour l’intégration 3D séquentielle

3D sequential integration is a promising candidate for the scaling sustainability for technological nodes beyond 14 nm. The main challenge is the development of a low temperature process for the top transistor level that enables to avoid the degradation of the bottom transistor level. The most critical process step for the top transistor level fabrication is the dopant activation that is usually performed at temperature higher than 1000 °C. In the frame of this Ph.D. work, different solutions for the dopant activation optimization at low temperature (below 600 °C) are proposed and integrated in FDSOI and TriGate devices. The technique chosen for the dopant activation at low temperature is the solid phase epitaxial regrowth. First, doping conditions have been optimized in terms of activation level and process time for low temperatures (down to 450 °C) anneals. The obtained conditions have been implemented in FDSOI and TriGate devices leading to degraded electrical results compared to the high temperature process of reference (above 1000 °C). By means of TCAD simulation and electrical measurements comparison, the critical region of the transistor in terms of activation appears to be below the offset spacer. The extension first integration scheme is then shown to be the best candidate to obtain high performance low temperature devices. Indeed, by performing the doping implantation before the raised source and drain epitaxial growth, the absence of diffusion at low temperature can be compensated. This conclusion can be extrapolated for TriGate and FinFET on insulator devices. Extension first integration scheme has been demonstrated for the first time on N and PFETs in 14 nm FDSOI technology showing promising results in terms of performance. This demonstration evidences that the two challenges of this integration i.e. the partial amorphization of very thin films and the epitaxy regrowth on implanted access are feasible. Finally, heated implantation has been investigated as a solution to dope thin access regions without full amorphization, which is particularly critical for FDSOI and FinFET devices. The as-implanted activation levels are shown to be too low to obtain high performance devices and the heated implantation appears a promising candidate for low temperature devices if used in combination with an alternative activation mechanism.L’intégration 3D séquentielle représente une alternative potentielle à la réduction des dimensions afin de gagner encore en densité d’une génération à la suivante. Le principal défi concerne la fabrication du transistor de l’étage supérieur avec un faible budget thermique; ceci afin d’éviter la dégradation du niveau inférieur. L’étape de fabrication la plus critique pour la réalisation du niveau supérieur est l’activation des dopants. Celle-ci est généralement effectuée par recuit à une température supérieure à 1000 °C. Dans ce contexte, cette thèse propose des solutions pour activer les dopants à des températures inférieures à 600 °C par la technique dite de recristallisation en phase solide. Les conditions de dopage ont été optimisées pour améliorer le niveau d’activation et le temps de recuit tout en réduisant la température d’activation jusqu’à 450°C. Les avancées obtenues ont été implémentées sur des dispositifs avancés FDSOI et TriGate générant des dispositifs avec des performances inférieures aux références fabriquées à hautes températures (supérieures à 1000 °C). En utilisant des simulations TCAD et en les comparant aux mesures électriques, nous avons montré que la région la plus critique en termes d’activation se trouve sous les espaceurs de la grille. Nous montrons alors qu’une intégration dite « extension first » est le meilleur compromis pour obtenir de bonnes performances sur des dispositifs fabriqués à faible température. En effet, l’implantation des dopants avant l’épitaxie qui vise à surélever les sources et drains compense l’absence de diffusion à basse température. Ces résultats ont par la suite été étendus pour des dispositifs TriGate et FinFETs sur isolants. Pour la première fois, l’intégration « extension first » a été démontrée pour des N et PFETs d’une technologie 14 nm FDSOI avec des résultats prometteurs en termes de performances. Les résultats obtenus montrent notamment qu’il est possible d’amorphiser partiellement un film très mince avant d’effectuer une recroissance épitaxiale sur une couche dopée. Finalement, une implantation ionique à relativement haute température (jusqu’à 500 °C) a été étudiée afin de doper les accès sans amorphiser totalement le film mince, ce qui est critique dans le cas des dispositifs FDSOI et FinFET. Nous montrons que les niveaux d’activation après implantation sont trop faibles pour obtenir des bonnes performances et que l’implantation ionique « chaude » est prometteuse à condition d’être utilisée avec un autre mécanisme d’activation comme le recuit laser

Filière technologique hybride InGaAs/SiGe pour applications CMOS

High-mobility channel materials such as indium-galium-arsenide (InGaAs) and silicon-germanium(SiGe) alloys are considered to be the leading candidates for replacing silicon (Si) in future lowpower complementary metal-oxide-semiconductor (CMOS) circuits. Numerous challenges haveto be tackled in order to turn the high-mobility CMOS concept into an industrial solution. Thisthesis addresses the majors challenges which are the integration of InGaAs on Si, the formationof high-quality gate stacks and self-aligned source and drain (S/D) regions, the optimizationof self-aligned transistors and the co-integration of InGaAs and SiGe into CMOS circuits. Allinvestigated possible solutions are proposed in the framework of very-large-scale integration requirements.Chapter 2 describes two different methods to integrate InGaAs on Si. Chapter 3 detailsthe developments of key process modules for the fabrication of self-aligned InGaAs metal-oxidesemiconductorfield-effect transistors (MOSFETs). Chapter 4 covers the realization of varioustypes of self-aligned MOSFETs towards the improvement of their performance. Finally, chapter5 demonstrates three different methods to make hybrid InGaAs/SiGe CMOS circuits.Les materiaux à forte mobilité comme l’InGaAs et le SiGe sont considérés comme des candidats potentiels pour remplacer le Si dans les circuits CMOS futurs. De nombreux défis doivent être surmontés pour transformer ce concept en réalité industrielle. Cette thèse couvre les principaux challenges que sont l’intégration de l’InGaAs sur Si, la formation d’oxydes de grille de qualité, la réalisation de régions source/drain auto-alignées de faible résistance, l’architecture des transistors ou encore la co-intégration de ces matériaux dans un procédé de fabrication CMOS.Les solutions envisagées sont proposées en gardant comme ligne directrice l’applicabilité des méthodes pour une production de grande envergure.Le chapitre 2 aborde l’intégration d’InGaAs sur Si par deux méthodes différentes. Le chapitre3 détaille le développement de modules spécifiques à la fabrication de transistors auto-alignés sur InGaAs. Le chapitre 4 couvre la réalisation de différents types de transistors auto-alignés sur InGaAs dans le but d’améliorer leurs performances. Enfin, le chapitre 5 présente trois méthodes différentes pour réaliser des circuits hybrides CMOS à base d’InGaAs et de SiGe

Electrical Characterisation of III-V Nanowire MOSFETs

The ever increasing demand for faster and more energy-efficient electricalcomputation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxidesemiconductorfield-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel.This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K.The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise measurements yielded border trap densities of 10^18 to 10^20 cm^-3 eV^-1 and hysteresis measurements yielded effective trap densities – projected to theoxide/semiconductor interface – of 2x10^12 to 3x10^13 cm^-2 eV^-1. Random telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band.Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs.Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits

Energy efficient core designs for upcoming process technologies

Energy efficiency has been a first order constraint in the design of micro processors for the last decade. As Moore's law sunsets, new technologies are being actively explored to extend the march in increasing the computational power and efficiency. It is essential for computer architects to understand the opportunities and challenges in utilizing the upcoming process technology trends in order to design the most efficient processors. In this work, we consider three process technology trends and propose core designs that are best suited for each of the technologies. The process technologies are expected to be viable over a span of timelines. We first consider the most popular method currently available to improve the energy efficiency, i.e. by lowering the operating voltage. We make key observations regarding the limiting factors in scaling down the operating voltage for general purpose high performance processors. Later, we propose our novel core design, ScalCore, one that can work in high performance mode at nominal Vdd, and in a very energy-efficient mode at low Vdd. The resulting core design can operate at much lower voltages providing higher parallel performance while consuming lower energy. While lowering Vdd improves the energy efficiency, CMOS devices are fundamentally limited in their low voltage operation. Therefore, we next consider an upcoming device technology -- Tunneling Field-Effect Transistors (TFETs), that is expected to supplement CMOS device technology in the near future. TFETs can attain much higher energy efficiency than CMOS at low voltages. However, their performance saturates at high voltages and, therefore, cannot entirely replace CMOS when high performance is needed. Ideally, we desire a core that is as energy-efficient as TFET and provides as much performance as CMOS. To reach this goal, we characterize the TFET device behavior for core design and judiciously integrate TFET units, CMOS units in a single core. The resulting core, called HetCore, can provide very high energy efficiency while limiting the slowdown when compared to a CMOS core. Finally, we analyze Monolithic 3D (M3D) integration technology that is widely considered to be the only way to integrate more transistors on a chip. We present the first analysis of the architectural implications of using M3D for core design and show how to partition the core across different layers. We also address one of the key challenges in realizing the technology, namely, the top layer performance degradation. We propose a critical path based partitioning for logic stages and asymmetric bit/port partitioning for storage stages. The result is a core that performs nearly as well as a core without any top layer slowdown. When compared to a 2D baseline design, an M3D core not only provides much higher performance, it also reduces the energy consumption at the same time. In summary, this thesis addresses one of the fundamental challenges in computer architecture -- overcoming the fact that CMOS is not scaling anymore. As we increase the computing power on a single chip, our ability to power the entire chip keeps decreasing. This thesis proposes three solutions aimed at solving this problem over different timelines. Across all our solutions, we improve energy efficiency without compromising the performance of the core. As a result, we are able to operate twice as many cores with in the same power budget as regular cores, significantly alleviating the problem of dark silicon