3D IC optimal layout design. A parallel and distributed topological approach

The task of 3D ICs layout design involves the assembly of millions of components taking into account many different requirements and constraints such as topological, wiring or manufacturability ones. It is a NP-hard problem that requires new non-deterministic and heuristic algorithms. Considering the time complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is superior to any other local search method. Nevertheless, it can often miss to reach a quasi-optimal solution in 3D spaces. The presented approach uses an original 3D layout graph partitioning heuristics implemented with use of the extremal optimization method. The goal is to minimize the total wire-length in the chip. In order to improve the time complexity a parallel and distributed Java implementation is applied. Inside one Java Virtual Machine separate optimization algorithms are executed by independent threads. The work may also be shared among different machines by means of The Java Remote Method Invocation system.Comment: 26 pages, 9 figure

Automatic synthesis and optimization of chip multiprocessors

The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental issue of power dissipation. Chip Multiprocessors (CMPs) have become the latest paradigm to improve the power-performance efficiency of computing systems by exploiting the parallelism inherent in applications. Industrial and prototype implementations have already demonstrated the benefits achieved by CMPs with hundreds of cores.CMP architects are challenged to take many complex design decisions. Only a few of them are:- What should be the ratio between the core and cache areas on a chip?- Which core architectures to select?- How many cache levels should the memory subsystem have?- Which interconnect topologies provide efficient on-chip communication?These and many other aspects create a complex multidimensional space for architectural exploration. Design Automation tools become essential to make the architectural exploration feasible under the hard time-to-market constraints. The exploration methods have to be efficient and scalable to handle future generation on-chip architectures with hundreds or thousands of cores.Furthermore, once a CMP has been fabricated, the need for efficient deployment of the many-core processor arises. Intelligent techniques for task mapping and scheduling onto CMPs are necessary to guarantee the full usage of the benefits brought by the many-core technology. These techniques have to consider the peculiarities of the modern architectures, such as availability of enhanced power saving techniques and presence of complex memory hierarchies.This thesis has several objectives. The first objective is to elaborate the methods for efficient analytical modeling and architectural design space exploration of CMPs. The efficiency is achieved by using analytical models instead of simulation, and replacing the exhaustive exploration with an intelligent search strategy. Additionally, these methods incorporate high-level models for physical planning. The related contributions are described in Chapters 3, 4 and 5 of the document.The second objective of this work is to propose a scalable task mapping algorithm onto general-purpose CMPs with power management techniques, for efficient deployment of many-core systems. This contribution is explained in Chapter 6 of this document.Finally, the third objective of this thesis is to address the issues of the on-chip interconnect design and exploration, by developing a model for simultaneous topology customization and deadlock-free routing in Networks-on-Chip. The developed methodology can be applied to various classes of the on-chip systems, ranging from general-purpose chip multiprocessors to application-specific solutions. Chapter 7 describes the proposed model.The presented methods have been thoroughly tested experimentally and the results are described in this dissertation. At the end of the document several possible directions for the future research are proposed

Enabling New Functionally Embedded Mechanical Systems Via Cutting, Folding, and 3D Printing

Traditional design tools and fabrication methods implicitly prevent mechanical engineers from encapsulating full functionalities such as mobility, transformation, sensing and actuation in the early design concept prototyping stage. Therefore, designers are forced to design, fabricate and assemble individual parts similar to conventional manufacturing, and iteratively create additional functionalities. This results in relatively high design iteration times and complex assembly strategies

Algorithms for Circuit Sizing in VLSI Design

One of the key problems in the physical design of computer chips, also known as integrated circuits, consists of choosing a  physical layout  for the logic gates and memory circuits (registers) on the chip. The layouts have a high influence on the power consumption and area of the chip and the delay of signal paths.  A discrete set of predefined layouts  for each logic function and register type with different physical properties is given by a library. One of the most influential characteristics of a circuit defined by the layout is its size. In this thesis we present new algorithms for the problem of choosing sizes for the circuits and its continuous relaxation,  and  evaluate these in theory and practice. A popular approach is based on Lagrangian relaxation and projected subgradient methods. We show that seemingly heuristic modifications that have been proposed for this approach can be theoretically justified by applying the well-known multiplicative weights algorithm. Subsequently, we propose a new model for the sizing problem as a min-max resource sharing problem. In our context, power consumption and signal delays are represented by resources that are distributed to customers. Under certain assumptions we obtain a polynomial time approximation for the continuous relaxation of the sizing problem that improves over the Lagrangian relaxation based approach. The new resource sharing algorithm has been implemented as part of the BonnTools software package which is developed at the Research Institute for Discrete Mathematics at the University of Bonn in cooperation with IBM. Our experiments on the ISPD 2013 benchmarks and state-of-the-art microprocessor designs provided by IBM illustrate that the new algorithm exhibits more stable convergence behavior compared to a Lagrangian relaxation based algorithm. Additionally, better timing and reduced power consumption was achieved on almost all instances. A subproblem of the new algorithm consists of finding sizes minimizing a weighted sum of power consumption and signal delays. We describe a method that approximates the continuous relaxation of this problem in polynomial time under certain assumptions. For the discrete problem we provide a fully polynomial approximation scheme under certain assumptions on the topology of the chip. Finally, we present a new algorithm for timing-driven optimization of registers. Their sizes and locations on a chip are usually determined during the clock network design phase, and remain mostly unchanged afterwards although the timing criticalities on which they were based can change. Our algorithm permutes register positions and sizes within so-called  clusters  without impairing the clock network such that it can be applied late in a design flow. Under mild assumptions, our algorithm finds an optimal solution which maximizes the worst cluster slack. It is implemented as part of the BonnTools and improves timing of registers on state-of-the-art microprocessor designs by up to 7.8% of design cycle time. </div

Parameterized macromodeling of passive and active dynamical systems

L'abstract è presente nell'allegato / the abstract is in the attachmen

visone - Software for the Analysis and Visualization of Social Networks

We present the software tool visone which combines graph-theoretic methods for the analysis of social networks with tailored means of visualization. Our main contribution is the design of novel graph-layout algorithms which accurately reflect computed analyses results in well-arranged drawings of the networks under consideration. Besides this, we give a detailed description of the design of the software tool and the provided analysis methods

Realization and Characterization of Metal-Semiconductor Field-Effect Transistors based on Amorphous Zinc Tin Oxide

Im ersten Teil der vorliegenden Arbeit werden die physikalischen Eigenschaften, insbesondere die elektrische Leitfähigkeit, von Zink-Zinn-Oxid Dünnschichten sowie darauf basierenden Schottky-Dioden in Abhängigkeit von der Kationenkomposition bestimmt. Zur Herstellung dieser Dünnschichten wurde ein Verfahren genutzt, welches die Herstellung von kontinuierlichen Kompositiongradienten im Rahmen eines gepulsten Laserabscheidungsprozesses bei Raumtemperatur ermöglicht. Erster Schwerpunkt der Diskussion ist die Abhängigkeit elektrischer Eigenschaften der Dünnschichten sowie die Diodeneigenschaften vom Kationenverhältnis. Des Weiteren wird die Langzeitstabilität der Schottky-Dioden und der Einfluss der Sauerstoffzufuhr während der Kontaktherstellung auf die Eigenschaften der Schottky-Dioden herausgestellt. DieErgebnissetiefenaufgelösterRöntgenphotoelektronenspektroskopiewerden diskutiert und ein Mechanismus, welcher zu einer Verbesserung der Schottky-Dioden über die Zeit führt, wird vorgestellt. Die Erkenntnisse über die optimale Kationenkomposition und den Einfluss des Sauerstoffs auf die Eigenschaften von Schottky-Dioden wurden genutzt, um Metall-Halbleiter-Feldeffekttransistoren herzustellen, welche im zweiten Teil der vorliegenden Arbeit beschrieben werden. In einem ersten Schritt wurden hierfür die Abscheidebedingungen in der Sputterkammer optimiert und eine neue Abscheiderezeptur für die Herstellung von Feldeffekttransistoren eingeführt. Auch hier finden alle Abscheidungen bei Raumtemperatur statt. Die Abscheidung mittels Sputtern wurde gewählt, da diese Abscheidemethode größere industrielle Relevanz als die gepulste Laserabscheidung hat. Metall-Halbleiter-Feldeffekttransistoren mit zwei verschiedenen Gate-Typen werden vorgestellt und jeweils der Einfluss der Kanalschichtdicke auf die Transistoreigenschaften untersucht. Der Einfluss des durch die Herstellung erzeugten Sauerstoffreservoirs in dem Schottky-Gate Kontakt auf die Eigenschaften der Feldeffekttransistoren wird ebenso gezeigt wie der Einfluss eines thermischen Ausheizprozesses auf die Schaltgeschwindigkeit der Feldeffekttransistoren. Außerdem werden einfache Inverter, welche auf zwei gleichartigen Feldeffekttransistoren basieren, vorgestellt. Ebenfalls werden SchottkyDioden Feldeffekttransistoren Logik basierte Inverter vorgestellt und charakterisiert. AbschließendwerdenRingoszillatoren,aufgebautausmehrereninReihegeschaltetenSchottkyDiodenFeldeffekttransistorenLogikbasiertenInverternvorgestellt. DerEinflussderKanalschichtdicke und der Gate-Geometrie auf die Oszillationsfrequenz wird diskutiert.:Contents 1 Introduction 2 Theoretical Descriptions 2.1 The Amorphous Semiconductor Zinc Tin Oxide 2.2 Schottky Barrier Diodes 2.3 Field-Effect Transistors 2.4 Inverter 2.5 Inverter Chain and Ring Oscillator 3 Methods 3.1 Growth and Structuring Techniques 3.1.1 Pulsed Laser Deposition 3.1.2 Sputtering Deposition 3.1.3 Photolithography 3.2 Characterization Techniques 3.2.1 Hall Effect Measurements 3.2.2 XRD and XRR Measurements 3.2.3 Static and Dynamic Current-Voltage Measurements 3.2.4 Further Characterization Techniques 4 Physical Properties of Amorphous Zinc Tin Oxide 4.1 Characterization of Pulsed Laser Deposited Zinc Tin Oxide Thin Films Having a Continuous Composition Spread 4.2 Properties of Schottky Barrier Diodes in Dependence on the Cation Composition 4.3 Long Term Stability of Schottky Barrier Diodes 4.4 ImportantRoleofOxygenfortheFormationofHighlyRectifyingContacts 4.5 Processes Governing the Long Term Stability 5 Demonstration and Characterization of Zinc Tin Oxide Based Devices 5.1 Implementation of a New Sputtering Recipe 5.1.1 CharacterizationandElectricalOptimizationoftheZincTinOxide Thin Films .1.2 Optimization of the Gate Contact 5.2 Devices with PtOx/Pt Gate Contact 5.2.1 Variation of the Channel Thickness 5.2.2 Influence of the Oxygen Reservoir on the Performance and Long Term Stability of Devices 5.2.3 Tuning of the Electron Mobility 5.2.4 Frequency Dependent Switching of Transistors 5.3 Devices with i-ZTO/PtOx/Pt Gate Contact 5.3.1 Transistors with Varying Channel Thickness 5.3.2 Simple Inverter 5.3.3 SDFL Inverter 5.3.4 Inverter Chain 5.3.5 Ring Oscillators 5.4 Comparison to Literature 6 Summary and Outlook Abbreviations List of Symbols Bibliography List of Own and Contributed Articles AppendixIn the first part of the present work the physical properties, especially the electrical properties, of zinc tin oxide thin films as well as Schottky diodes based thereon are determined as a function of the cation composition. For film growth, a room temperature pulsed laser deposition process was used, which allows the realization of a continuous composition gradient within one sample. First focus of the discussion is the dependence of electrical properties of thin films as well as diode properties on the cation ratio. Furthermore, the long-term stability of the Schottky diodes and the influence of the oxygen supply during contact fabrication on the properties of the Schottky diodes are highlighted. The results of depth-resolved Xray photoelectron spectroscopy measurements are discussed and a mechanism leading to an improvement of the Schottky diodes over time is elucidated. The findings on the optimal cation composition and the influence of oxygen on the properties of Schottky diodes were used to produce metal-semiconductor field-effect transistors, which are described in the second part of this thesis. In a first step, the deposition conditions in the sputter chamber were optimized and a new deposition recipe for the fabrication of field effect transistors was developed. Here, too, all depositions take place at room temperature. Sputter deposition was chosen because this deposition method has greater industrial relevance than pulsed laser deposition. Metal-semiconductor field-effect-transistors with two different gate types are presented and the influence of the channel layer thickness on the transistor properties is investigated. The influence of the oxygen reservoir in the Schottky gate contact on the properties of the field-effect-transistors is shown as well as the influence of a thermal annealing process on the switching speed of the field-effect-transistors. In addition, simple inverters based on two identical field-effect-transistors are demonstrated. Also Schottky diode field-effect-transistor logic based inverters are presented and characterized. Finally, ring oscillators consisting of several series-connected Schottky diode field-effecttransistor logic based inverters are presented. The influence of channel layer thickness and gate geometry on the oscillation frequency is discussed.:Contents 1 Introduction 2 Theoretical Descriptions 2.1 The Amorphous Semiconductor Zinc Tin Oxide 2.2 Schottky Barrier Diodes 2.3 Field-Effect Transistors 2.4 Inverter 2.5 Inverter Chain and Ring Oscillator 3 Methods 3.1 Growth and Structuring Techniques 3.1.1 Pulsed Laser Deposition 3.1.2 Sputtering Deposition 3.1.3 Photolithography 3.2 Characterization Techniques 3.2.1 Hall Effect Measurements 3.2.2 XRD and XRR Measurements 3.2.3 Static and Dynamic Current-Voltage Measurements 3.2.4 Further Characterization Techniques 4 Physical Properties of Amorphous Zinc Tin Oxide 4.1 Characterization of Pulsed Laser Deposited Zinc Tin Oxide Thin Films Having a Continuous Composition Spread 4.2 Properties of Schottky Barrier Diodes in Dependence on the Cation Composition 4.3 Long Term Stability of Schottky Barrier Diodes 4.4 ImportantRoleofOxygenfortheFormationofHighlyRectifyingContacts 4.5 Processes Governing the Long Term Stability 5 Demonstration and Characterization of Zinc Tin Oxide Based Devices 5.1 Implementation of a New Sputtering Recipe 5.1.1 CharacterizationandElectricalOptimizationoftheZincTinOxide Thin Films .1.2 Optimization of the Gate Contact 5.2 Devices with PtOx/Pt Gate Contact 5.2.1 Variation of the Channel Thickness 5.2.2 Influence of the Oxygen Reservoir on the Performance and Long Term Stability of Devices 5.2.3 Tuning of the Electron Mobility 5.2.4 Frequency Dependent Switching of Transistors 5.3 Devices with i-ZTO/PtOx/Pt Gate Contact 5.3.1 Transistors with Varying Channel Thickness 5.3.2 Simple Inverter 5.3.3 SDFL Inverter 5.3.4 Inverter Chain 5.3.5 Ring Oscillators 5.4 Comparison to Literature 6 Summary and Outlook Abbreviations List of Symbols Bibliography List of Own and Contributed Articles Appendi

Structure discovery techniques for circuit design and process model visualization

Graphs are one of the most used abstractions in many knowledge fields because of the easy and flexibility by which graphs can represent relationships between objects. The pervasiveness of graphs in many disciplines means that huge amounts of data are available in graph form, allowing many opportunities for the extraction of useful structure from these graphs in order to produce insight into the data. In this thesis we introduce a series of techniques to resolve well-known challenges in the areas of digital circuit design and process mining. The underlying idea that ties all the approaches together is discovering structures in graphs. We show how many problems of practical importance in these areas can be solved utilizing both common and novel structure mining approaches. In the area of digital circuit design, this thesis proposes automatically discovering frequent, repetitive structures in a circuit netlist in order to improve the quality of physical planning. These structures can be used during floorplanning to produce regular designs, which are known to be highly efficient and economical. At the same time, detecting these repeating structures can exponentially reduce the total design time. The second focus of this thesis is in the area of the visualization of process models. Process mining is a recent area of research which centers on studying the behavior of real-life systems and their interactions with the environment. Complicated process models, however, hamper this goal. By discovering the important structures in these models, we propose a series of methods that can derive visualization-friendly process models with minimal loss in accuracy. In addition, and combining the areas of circuit design and process mining, this thesis opens the area of specification mining in asynchronous circuits. Instead of the usual design flow, which involves synthesizing circuits from specifications, our proposal discovers specifications from implemented circuits. This area allows for many opportunities for verification and re-synthesis of asynchronous circuits. The proposed methods have been tested using real-life benchmarks, and the quality of the results compared to the state-of-the-art.Els grafs són una de les representacions abstractes més comuns en molts camps de recerca, gràcies a la facilitat i flexibilitat amb la que poden representar relacions entre objectes. Aquesta popularitat fa que una gran quantitat de dades es puguin trobar en forma de graf, i obre moltes oportunitats per a extreure estructures d'aquest grafs, útils per tal de donar una intuïció millor de les dades subjacents. En aquesta tesi introduïm una sèrie de tècniques per resoldre reptes habitualment trobats en les àrees de disseny de circuits digitals i mineria de processos industrials. La idea comú sota tots els mètodes proposats es descobrir automàticament estructures en grafs. En la tesi es mostra que molts problemes trobats a la pràctica en aquestes àrees poden ser resolts utilitzant nous mètodes de descobriment d'estructures. En l'àrea de disseny de circuits, proposem descobrir, automàticament, estructures freqüents i repetitives en les definicions del circuit per tal de millorar la qualitat de les etapes posteriors de planificació física. Les estructures descobertes poden fer-se servir durant la planificació per produir dissenys regulars, que son molt més econòmics d'implementar. Al mateix temps, la descoberta i ús d'aquestes estructures pot reduir exponencialment el temps total de disseny. El segon punt focal d'aquesta tesi és en l'àrea de la visualització de models de processos industrials. La mineria de processos industrials es un tema jove de recerca que es centra en estudiar el comportament de sistemes reals i les interaccions d'aquests sistemes amb l'entorn. No obstant, quan d'aquest anàlisi s'obtenen models massa complexos visualment, l'estudi n'és problemàtic. Proposem una sèrie de mètodes que, gràcies al descobriment automàtic de les estructures més importants, poden generar models molt més fàcils de visualitzar que encara descriuen el comportament del sistema amb gran precisió. Combinant les àrees de disseny de circuits i mineria de processos, aquesta tesi també obre un nou tema de recerca: la mineria d'especificacions per circuits asíncrons. En l'estil de disseny asíncron habitual, sintetitzadors automàtics generen circuits a partir de les especificacions. En aquesta tesi proposem el pas invers: descobrir automàticament les especificacions de circuits ja implementats. Així, creem noves oportunitats per a la verificació i la re-síntesi de circuits asíncrons. Els mètodes proposats en aquesta tesi s'han validat fent servir dades obtingudes d'aplicacions pràctiques, i en comparem els resultats amb els mètodes existents