Optimal I-V

High-efficiency solar cells and modules exhibit strong capacitive character resulting in limited speed of transient responses. A too fast I-V curve measurement can thus introduce a significant error due to its internal capacitances. This paper analyses the I-V curve error of a measured solar cell or module in light of scan time and irradiance level. It rests on a two-diode solar cell model extended by two bias-dependent capacitances, modelling the junction, and the diffusion capacitance. A method for determination of all extended model parameters from a quasistatic I-V curve and open-circuit voltage decay measurement is presented and validated. Applicability of the extended model and the developed parameter extraction method to PV modules is demonstrated and confirmed. SPICE simulations of the extended model are used to obtain the I-V curve error versus scan time dependence and the I-V curve hysteresis. Determination of the optimal scan time is addressed, and finally the influence of the irradiance level on the I-V curve scan time and error is revealed. The method is applied but is not limited to three different wafer-based silicon solar cell types

FIT-2, an extraction program based on the SPICE-PAC simulation software

FIT-2, an interactive program for extraction of transistor parameters for SPICE-like circuit simulators, is discussed. It is based on a circuit simulator rather than on an explicit set of model equations. Several optimization methods are built into the program to provide robust as well as sufficient fitting of device characteristics. The flexibility of the approach is obtained by specification of extraction details in the data sets rather than the extraction procedure. Extraction results for heterojunction bipolar transistors are used as an illustration of FIT-2's capabilities. Several directions for further research are identified

FIT–2, A SIMULATION–BASED PARAMETER EXTRACTION PROGRAM

Accurate and reliable simulation of circuit behavior cannot be obtained without ade- quate device models. FIT–2 is an interactive program for extraction of transistor parameters for SPICE–like circuit simulators. It is based on a circuit simulator rather than an explicit set of model equations. Basic advantages of the proposed approach include: (1) explicit model equations need not be known as they are provided by the circuit simulation tool used, (2) fitting can be performed not only for single devices but for functional blocks or whole circuits as well, and (3) the same extractor can be used for a variety of devices and/or device models. Several optimization methods are built into the program to provide robust as well as efficient fitting of device characteristics. Flexibility of the approach is obtained by specification of extraction details in the data sets rather than the extraction procedure. Parameter extraction for heterojunction bipolar transistors (HBT) is used as an illustration of FIT-2 capabilities. The effects of optimization methods on extraction performance are presented. Several directions for further research are identified

Optimisation of flow chemistry: tools and algorithms

The coupling of flow chemistry with automated laboratory equipment has become increasingly common and used to support the efficient manufacturing of chemicals. A variety of reactors and analytical techniques have been used in such configurations for investigating and optimising the processing conditions of different reactions. However, the integrated reactors used thus far have been constrained to single phase mixing, greatly limiting the scope of reactions for such studies. This thesis presents the development and integration of a millilitre-scale CSTR, the fReactor, that is able to process multiphase flows, thus broadening the range of reactions susceptible of being investigated in this way. Following a thorough review of the literature covering the uses of flow chemistry and lab-scale reactor technology, insights on the design of a temperature-controlled version of the fReactor with an accuracy of ±0.3 ºC capable of cutting waiting times 44% when compared to the previous reactor are given. A demonstration of its use is provided for which the product of a multiphasic reaction is analysed automatically under different reaction conditions according to a sampling plan. Metamodeling and cross-validation techniques are applied to these results, where single and multi-objective optimisations are carried out over the response surface models of different metrics to illustrate different trade-offs between them. The use of such techniques allowed reducing the error incurred by the common least squares polynomial fitting by over 12%. Additionally, a demonstration of the fReactor as a tool for synchrotron X-Ray Diffraction is also carried out by means of successfully assessing the change in polymorph caused by solvent switching, this being the first synchrotron experiment using this sort of device. The remainder of the thesis focuses on applying the same metamodeling and cross-validation techniques used previously, in the optimisation of the design of a miniaturised continuous oscillatory baffled reactor. However, rather than using these techniques with physical experimentation, they are used in conjunction with computational fluid dynamics. This reactor shows a better residence time distribution than its CSTR counterparts. Notably, the effect of the introduction of baffle offsetting in a plate design of the reactor is identified as a key parameter in giving a narrow residence time distribution and good mixing. Under this configuration it is possible to reduce the RTD variance by 45% and increase the mixing efficiency by 60% when compared to the best performing opposing baffles geometry

FIT-S, a simulation-based data-driven parameter extraction program

FIT–S is an interactive program for extraction of device parameters for SPICE–like circuit simulators. It is based on a circuit simulator rather than an explicit set of model equations. Basic advantages of the proposed approach include: (1) explicit model equations need not be known as they are provided by the circuit simulation tool used, (2) fitting can be performed not only for single devices but for functional blocks or whole circuits as well, and (3) the same extractor can be used for a variety of devices and/or device models. The extractor supports numerical as well as symbolic simulation so repeated analyses of linearized circuit (for frequency domain analyses) can be performed very efficiently using the symbolic functions generated from the Coates flowgraph representation of the circuit. Several optimization methods are built into the program to provide robust as well as efficient fitting of device characteristics. Flexibility of the approach is obtained by specification of extraction details in the data sets rather than the extraction procedure. Parameter extraction for heterojunction bipolar transistors (HBT) is used as an illustration of FIT–S capabilities

Developement of simulation tools for the analysis of variability in advanced semiconductor electron devices

The progressive down-scaling has been the driving force behind the integrated circuit (IC) industry for several decades, continuously delivering higher component densities and greater chip functionality, while reducing the cost per function from one CMOS technology generation to the next. Moore’s law boosts IC industry profits by constantly releasing high-quality and inexpensive electronic applications into the market using new technologies. From the 1 m gate lengths of the eighties to the 35 nm gate lengths of contemporary 22 nm technology, the industry successfully achieved its scaling goals, not only miniaturizing devices but also improving device performance

Fast and Robust Design of CMOS VCO for Optimal Performance

The exponentially growing design complexity with technological advancement calls for a large scope in the analog and mixed signal integrated circuit design automation. In the automation process, performance optimization under different environmental constraints is of prime importance. The analog integrated circuits design strongly requires addressing multiple competing performance objectives for optimization with ability to find global solutions in a constrained environment. The integrated circuit (IC) performances are significantly affected by the device, interconnect and package parasitics. Inclusion of circuit parasitics in the design phase along with performance optimization has become a bare necessity for faster prototyping. Besides this, the fabrication process variations have a predominant effect on the circuit performance, which is directly linked to the acceptability of manufactured integrated circuit chips. This necessitates a manufacturing process tolerant design. The development of analog IC design methods exploiting the computational intelligence of evolutionary techniques for optimization, integrating the circuit parasitic in the design optimization process in a more meaningful way and developing process fluctuation tolerant optimal design is the central theme of this thesis. Evolutionary computing multi-objective optimization techniques such as Non-dominated Sorting Genetic Algorithm-II and Infeasibility Driven Evolutionary Algorithm are used in this thesis for the development of parasitic aware design techniques for analog ICs. The realistic physical and process constraints are integrated in the proposed design technique. A fast design methodology based on one of the efficient optimization technique is developed and an extensive worst case process variation analysis is performed. This work also presents a novel process corner variation aware analog IC design methodology, which would effectively increase the yield of chips in the acceptable performance window. The performance of all the presented techniques is demonstrated through the application to CMOS ring oscillators, current starved and xi differential voltage controlled oscillators, designed in Cadence Virtuoso Analog Design Environment

Symbolic analysis in parameter extraction, its implementation and performance

An interface between a symbolic analysis tool and a SPICE–like circuit simulation pack- age has been developed in order to integrate numerical and symbolic circuit analyses. In effect, both numerical and symbolic analyses use the same internal representation of circuits which makes the two approaches truly complementary. This integrated simulation capabil- ity is used in simulation–based parameter extraction where all ac small-signal parameters are fitted through the symbolic analysis rather than numerical one, significantly reducing the execution time of the extraction process

DYNAMIC RANGE LIMITATIONS OF LOW-NOISE MICROWAVE TRANSISTORS AT CRYOGENIC TEMPERATURES

Dynamic range is an important metric that specifies the limits of input signal amplitude for the ideal operation of a given receiver. The low end of dynamic range is defined by the noise floor whereas the upper limit is determined by large-signal distortion. While dynamic range can be predicted in the temperature range where compact transistor models are valid, the lack of large-signal models at temperatures below -55 C prevents the prediction and optimization of dynamic range for applications that require cryogenic cooling. For decades, the main goal concerning the performance of these applications was lowering the noise floor of cryogenic receiver front-ends. For this, linear small-signal noise models have been extensively studied and used for designs of low-noise amplifiers. In this work, the existing small-signal noise modeling approach is extended to capture the weakly nonlinear properties of the transistors that are commonly used in cryogenic amplification. Indium phosphide high electron mobility transistors and silicon germanium heterojunction bipolar transistors are considered. The goal of this work is to identify the fundamental dynamic range limitations of these transistors such that the results are not device specific, but applicable to the corresponding device families. Identifying the fundamental limitations of dynamic range in a semiconductor device requires a broad understanding of physical properties of the transistors. For this, a theoretical analysis will be presented first as a function of temperature. The small-signal noise modeling will then be discussed using techniques that are well recognized in the literature. This will be followed by an explanation of the nonlinear modeling approach used in this work. This approach relies on the definition of Taylor series expansion coefficients of the dominant nonlinear mechanisms of the transistors. The modeling results will be interpreted with respect to the initially presented theoretical framework. Finally, the dynamic range performance will be studied as a function of source and load terminations. In addition to this systematic approach to understanding the physical limitations of dynamic range, model to measurement agreement of broadband cryogenic amplifiers will also be presented which will verify the accuracy of the modeling approach

Novel Application of Fast Simulated Annealing Method in Brushless Motor Drive (BLMD) Dynamical Parameter Identification for Electric Vehicle Propulsion

Permanent magnet brushless motor drives (BLMD) are extensively used in electric vehicle (EV) propulsion systems because of their high power and torque to weight ratio, virtually maintenance free operation with precision control of torque, speed and position. An accurate dynamical parameter identification strategy is an essential feature in the adaptive control of such BLMD-EV systems where sensorless current feedback is employed for reliable torque control, with multi-modal penalty cost surfaces, in EV high performance tracking and target ranging. Application of the classical Powell Conjugate Direction optimization method is first discussed and its inaccuracy in dynamical parameter identification is illustrated for multimodal cost surfaces. This is used for comparison with the more accurate Fast Simulated Annealing/Diffusion (FSD) method, presented here, in terms of the returned parameter estimates. Details of the FSD development and application to the BLMD parameter estimation problem based on the minimum quantized parameter step sizes from noise considerations are provided. The accuracy of global parameter convergence estimates returned, cost function evaluation and the algorithm run time are presented. Validation of the FSD identification strategy is provided by excellent correlation of BLMD model simulation trace coherence with experimental test data at the optimal estimates and from cost surface simulation