145 research outputs found
Extensions to the CEGAR approach on Petri nets
Formal verification is becoming more prevalent and often compulsory in the safety-critical system and software development processes. Reachability analysis can provide information about safety and invariant properties of the developed system. However, checking the reachability is a computationally hard problem, especially in the case of asynchronous or infinite state systems. Petri nets are widely used for the modeling and verification of such systems. In this paper we examine a recently published approach for the reachability checking of Petri net markings. We give proofs concerning the completeness and the correctness properties of the algorithm, and we introduce algorithmic improvements. We also extend the algorithm to handle new classes of problems: submarking coverability and reachability of Petri nets with inhibitor arcs
Approaching the Coverability Problem Continuously
The coverability problem for Petri nets plays a central role in the
verification of concurrent shared-memory programs. However, its high
EXPSPACE-complete complexity poses a challenge when encountered in real-world
instances. In this paper, we develop a new approach to this problem which is
primarily based on applying forward coverability in continuous Petri nets as a
pruning criterion inside a backward coverability framework. A cornerstone of
our approach is the efficient encoding of a recently developed polynomial-time
algorithm for reachability in continuous Petri nets into SMT. We demonstrate
the effectiveness of our approach on standard benchmarks from the literature,
which shows that our approach decides significantly more instances than any
existing tool and is in addition often much faster, in particular on large
instances.Comment: 18 pages, 4 figure
Improving explicit model checking for Petri nets
Model checking is the automated verification that systematically checks if a given behavioral property holds for a given model of a system. We use Petri nets and temporal logic as formalisms to describe a system and its behavior in a mathematically precise and unambiguous manner. The contributions of this thesis are concerned with the improvement of model checking efficiency both in theory and in practice. We present two new reduction techniques and several supplementary strength reduction techniques. The thesis also enhances partial order reduction for certain temporal logic classes
Verification and Parameter Synthesis for Real-Time Programs using Refinement of Trace Abstraction
We address the safety verification and synthesis problems for real-time
systems. We introduce real-time programs that are made of instructions that can
perform assignments to discrete and real-valued variables. They are general
enough to capture interesting classes of timed systems such as timed automata,
stopwatch automata, time(d) Petri nets and hybrid automata.
We propose a semi-algorithm using refinement of trace abstractions to solve
both the reachability verification problem and the parameter synthesis problem
for real-time programs.
All of the algorithms proposed have been implemented and we have conducted a
series of experiments, comparing the performance of our new approach to
state-of-the-art tools in classical reachability, robustness analysis and
parameter synthesis for timed systems. We show that our new method provides
solutions to problems which are unsolvable by the current state-of-the-art
tools
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