1,595 research outputs found
SpinLink: An interconnection system for the SpiNNaker biologically inspired multi-computer
SpiNNaker is a large-scale biologically-inspired multi-computer designed to model very heavily distributed problems, with the flagship application being the simulation of large neural networks. The project goal is to have one million processors included in a single machine, which consequently span many thousands of circuit boards. A computer of this scale imposes large communication requirements between these boards, and requires an extensible method of connecting to external equipment such as sensors, actuators and visualisation systems. This paper describes two systems that can address each of these problems.Firstly, SpinLink is a proposed method of connecting the SpiNNaker boards by using time-division multiplexing (TDM) to allow eight SpiNNaker links to run at maximum bandwidth between two boards. SpinLink will be deployed on Spartan-6 FPGAs and uses a locally generated clock that can be paused while the asynchronous links from SpiNNaker are sending data, thus ensuring a fast and glitch-free response. Secondly, SpiNNterceptor is a separate system, currently in the early stages of design, that will build upon SpinLink to address the important external I/O issues faced by SpiNNaker. Specifically, spare resources in the FPGAs will be used to implement the debugging and I/O interfacing features of SpiNNterceptor
On Making Emerging Trusted Execution Environments Accessible to Developers
New types of Trusted Execution Environment (TEE) architectures like TrustLite
and Intel Software Guard Extensions (SGX) are emerging. They bring new features
that can lead to innovative security and privacy solutions. But each new TEE
environment comes with its own set of interfaces and programming paradigms,
thus raising the barrier for entry for developers who want to make use of these
TEEs. In this paper, we motivate the need for realizing standard TEE interfaces
on such emerging TEE architectures and show that this exercise is not
straightforward. We report on our on-going work in mapping GlobalPlatform
standard interfaces to TrustLite and SGX.Comment: Author's version of article to appear in 8th Internation Conference
of Trust & Trustworthy Computing, TRUST 2015, Heraklion, Crete, Greece,
August 24-26, 201
A Catalog of Hardware Acceleration Techniques for Real-Time Reconfigurable System on Chip
The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of real-time embedded systems. In particular, the judicious use of specialised data processing peripherals can reduce the CPU load significantly and greatly ease the task of guaranteeing that real-time deadlines are met in complex multi-processing real-time systems. A catalog of other possible uses for the reconfigurable logic resources on such a chip which can assist in improving real-time system performance is also presented
The Glasgow raspberry pi cloud: a scale model for cloud computing infrastructures
Data Centers (DC) used to support Cloud services
often consist of tens of thousands of networked machines under a single roof. The significant capital outlay required to replicate such infrastructures constitutes a major obstacle to practical implementation and evaluation of research in this domain. Currently, most research into Cloud computing relies on either limited software simulation, or the use of a testbed environments
with a handful of machines. The recent introduction of the
Raspberry Pi, a low-cost, low-power single-board computer, has made the construction of a miniature Cloud DCs more affordable.
In this paper, we present the Glasgow Raspberry Pi Cloud
(PiCloud), a scale model of a DC composed of clusters of
Raspberry Pi devices. The PiCloud emulates every layer of a
Cloud stack, ranging from resource virtualisation to network
behaviour, providing a full-featured Cloud Computing research and educational environment
Egret: A platform for reconfigurable system-on-chip
Reconfigurable System-on-Chip (rSoC) design is inherently a complex task with enormous freedom in design parameters such as processor, operating system, and backplane buses. Design efficiency can be improved by the use of an rSoC platform which constrains these choices, and allows new designs to leverage much of the expertise of previous designs. Egret is an rSoC prototyping platform being developed at the University of Queensland, Australia, and this paper explains and justifies the design decisions for the first version of Egret
QYPS HPS Interconnect verification methodology for SOC FPGA
FPGA yang mengandungi unit pemprosesan terbenam adalah aliran masa depan bagi aplikasi-aplikasi berprestasi tinggi dan berkuasa rendah. Saling-sambung HPS Qsys, telah direka untuk menyambungkan FPGA dengan sistem pemprosesan terbenam (HPS) melalui satu klik tetikus. Walaupun, model berfungsi bas (BFM) sering digunakan bagi metodologi pengesahan untuk saling-sambung Qsys, HPS melibatkan protocol-protokol antaramuka yang berbeza. Tugas untuk merekabentuk dan mengesahkan BFM akan mengambil masa yang panjang. Oleh itu, metodologi pengesahan yang baru telah dicadangkan untuk saling-sambung HPS Qsys di dalam projek penyelidikan ini. Bagi kaedah pengesahan yang dicadangkan, saling-sambung HPS Qsys akan digabungkan ke dalam bangku ujian pengesahan HPS RTL melalui sejenis rekabentuk suis pin. Selain itu, rekabentuk Qsys juga digabungkan ke dalam simulasi ujian HPS RTL. Lima antaramuka Qsys, iaitu UART, SPI, FPGA-CTI, FPGA interrupt dan boot-from-FPGA telah berjaya disahkan melalui metodologi pengesahan yang dicadangkan. Berbanding dengan ujian pengesahan HPS RTL, masa simulasi yang lebih pendek telah diperhatikan semasa menguji fungsi yang sama dalam cadangan kaedah pengesahan.
Field programmable gate array (FPGA) with embedded processor is the future trend for the high performance and low power applications. Qsys HPS interconnect is designed to provide seamless connection between FPGA and the embedded hard processor system (HPS) through a click of mouse. Although bus functional model (BFM) is extensively used in existing Qsys non-HPS interconnect verification methodology, HPS consists of many different interface protocols. The task of develop and validate the BFMs become the bottleneck in verification. A new Qsys HPS interconnect verification methodology has been proposed in this research project. In the proposed verification methodology, the Qsys HPS interconnect will be integrated into HPS RTL verification test bench through a pin switch architecture. Besides, the Qsys design is also integrated into HPS RTL simulation test flow. Five different Qsys interface designs, namely UART, SPI, FPGA-CTI, FPGA interrupt and boot-from-FPGA have been successfully verified using the proposed verification methodology. Shorter simulation time has been observed while testing same function in the proposed verification methodology as compared to HPS RTL verification test
High level modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE
International audienceSystem-on-Chip (SoC) architectures are becoming the preferred solution for implementing modern embedded systems. However their design complexity continues to augment due to the increase in integrated hardware resources requiring new design methodologies and tools. In this paper we present a novel SoC co-design methodology based on aModel Driven Engineering framework while utilizing the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology permits us to model fine grain reconfigurable architectures such as FPGAs and allows to extend the standard for integrating new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The overall objective is to carry out modeling at a high abstraction level expressed in a graphical language like UML (Unified Modeling Language) and afterwards transformations of these models, automatically generate the necessary specifications required for FPGA implementation
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