Distributed Services with Foreseen and Unforeseen Tasks: The Mobile Re-allocation Problem

In this paper we deal with a common problem found in the operations of security and preventive/corrective maintenance services: that of routing a number of mobile resources to serve foreseen and unforeseen tasks during a shift. We define the (Mobile Re-Allocation Problem) MRAP as the problem of devising a routing strategy to maximize the expected weighted number of tasks served on time. For obtaining a solution to the MRAP, we propose to solve successively a multi-objective optimization problem called the stochastic Team Orienteering Problem with Multiple Time Windows (s-TOP-MTW) so as to consider information about known tasks and the arrival process of new unforeseen tasks. Solving successively the s-TOP-MTW we find that considering information about the arrival process of new unforeseen tasks may aid in maximizing the expected proportion of tasks accomplished on time.location;reliability;routing;distributed services

SimpleSSD: Modeling Solid State Drives for Holistic System Simulation

Existing solid state drive (SSD) simulators unfortunately lack hardware and/or software architecture models. Consequently, they are far from capturing the critical features of contemporary SSD devices. More importantly, while the performance of modern systems that adopt SSDs can vary based on their numerous internal design parameters and storage-level configurations, a full system simulation with traditional SSD models often requires unreasonably long runtimes and excessive computational resources. In this work, we propose SimpleSSD, a highfidelity simulator that models all detailed characteristics of hardware and software, while simplifying the nondescript features of storage internals. In contrast to existing SSD simulators, SimpleSSD can easily be integrated into publicly-available full system simulators. In addition, it can accommodate a complete storage stack and evaluate the performance of SSDs along with diverse memory technologies and microarchitectures. Thus, it facilitates simulations that explore the full design space at different levels of system abstraction.Comment: This paper has been accepted at IEEE Computer Architecture Letters (CAL

Feasibility analysis of establishing charging stations for electrical vehicles in public facilities

To overcome the transportation sector\u27s dependency on fossil fuels, electric vehicles appears to be a better alternative with a number of impressive benefits. Enhancing the utilization of electric vehicles not only reduces global gasoline and diesel consumption but also helps in running an environmentally cleaner road transport system with zero tailpipe emissions. As road transport involves substantial gasoline and diesel consumption, Plug-in Electric Vehicles (EVs) being more energy efficient and environment friendly can have direct impact on reduction of fuel reliance. One of the important limitations influencing the penetration of electrical vehicles in the global market is the lack of adequate charging infrastructure availability. Considering various challenges involved in deployment of charging infrastructure, enhancement of public charging infrastructure can be a successful step resulting in electric vehicle market raise. This project is focused in developing a decision support system to evaluate optimal number of charging stations to be established in a public facility, which are sustainable and economically viable. This system considers a Monte Carlo simulation of a scenario using various pre-recorded categorical data, depicting traffic arrival patterns and logistic challenges created by variance in weather severity and time of the year. The simulated data can be used to estimate the energy consumption and costs incurred by the charging stations in the facility. This work results in a decision making spreadsheet-based model that enable facilities to explore cost implications of installing and operating Electric Vehicle Supply Equipment (EVSE)

Supporting Service Differentiation with Enhancements of the IEEE 802.11 MAC Protocol: Models and Analysis

As one of the fastest growing wireless access technologies, Wireless LANs must evolve to support adequate degrees of service differentiation. Unfortunately, current WLAN standards like IEEE 802.11 Distributed Coordination Function (DCF) lack this ability. Work is in progress to define an enhanced version capable of supporting QoS for multimedia traffic at the MAC layer. In this paper, we aim at gaining insight into three mechanisms to differentiate among traffic categories, i.e., differentiating the minimum contention window size, the Inter-Frame Spacing (IFS) and the length of the packet payload according to the priority of different traffic categories. We propose an analysis model to compute the throughput and packet transmission delays. In additions, we derive approximations to get simpler but more meaningful relationships among different parameters. Comparisons with discrete-event simulation results show that a very good accuracy of performance evaluation can be achieved by using the proposed analysis model

Predictable and composable system-on-chip memory controllers

Contemporary System-on-Chip (SoC) become more and more complex, as increasing integration results in a larger number of concurrently executing applications. These applications consist of tasks that are mapped on heterogeneous multi-processor platforms with distributed memory hierarchies, where SRAMs and SDRAMs are shared by a variety of arbiters. Some applications have real-time requirements, meaning that they must perform a particular computation before a deadline to guarantee functional correctness, or to prevent quality degradation. Mapping the applications on the platform such that all real-time requirements are satisfied is very challenging. The number of possible mappings of tasks to processing elements and data structures to memories may be large, and appropriate configuration settings must be determined once the mapping is chosen. Verifying that a particular mapping satisfies all application requirements is typically done by system-level simulation. However, resource sharing causes interference between applications, making their temporal behaviors inter-dependent. All concurrently executing applications must hence be verified together, causing the verification complexity of the system to increase exponentially with the number of applications. Together these factors contribute to making the integration and verification process a dominant part of SoC development, both in terms of time and money. Predictable and composable systems are proposed to manage the increasing verification complexity. Predictable systems provide lower bounds on application performance, while applications in composable systems are completely isolated and cannot affect each other’s temporal behavior by even a single clock cycle. Predictable systems enable formal verification that covers all possible interactions with the platform. However, this assumes that the behavior of an application is captured in a performance model, which is not the case for many applications. Composability offers a complementary verification approach by letting these applications be verified independently by simulation with linear verification complexity. A limitation of current predictable and composable systems is that there are no memory controllers supporting the concepts in a general way. Current SRAM controllers can be shared in a predictable way with a variety of arbiters, but are only composable if statically scheduled or shared using time-division multiplexing. Existing SDRAM controllers are not composable, and are either unpredictable or limited to applications that are statically scheduled. This thesis addresses the limitations of current predictable and composable systems by proposing a general predictable and composable memory controller, thereby addressing the mapping and verification problem in embedded systems. The proposed memory controller is divided into a front-end and a back-end. The back-end is specific for DDR2/DDR3 SDRAM and makes the memory behave in a predictable manner using precomputed memory patterns that are dynamically combined at run time. The front-end contains buffering and an arbiter in the class of Latency-Rate (LR) servers, which is a class with many well-known predictable arbiters. We extend this class with a Credit-Controlled Static-Priority (CCSP) arbiter that is developed specifically for shared resources with latency-critical requestors and high loads, such as memories. Three key features of CCSP are: 1) It accommodates latency-critical requestors with low bandwidth requirements without wasting bandwidth. 2) Over-allocated bandwidth can be made negligible at an increased area cost, without affecting latency. 3) It has a small implementation that runs fast enough to keep up with most DDR2/DDR3 memories. The proposed front-end is general and can be used with other predictable resources, such as SRAM controllers. The proposed memory controller hence supports multiple arbiter and memory types, thus addressing the diversity in modern SoCs. The combination of front-end and predictable memory behaves like a LR server, which is the shared resource abstraction used in this work. In essence, a LR server guarantees a requestor a minimum bandwidth and a maximum latency, enabling formal verification of real-time requirements. The LR server model is compatible with several commonly used formal analysis frameworks, such as network calculus and data-flow analysis. Our memory controller hence allows any combination of predictable memory and LR arbiter to be used transparently for formal verification of applications with any of these frameworks. Sharing a predictable memory at run-time results in interference between requestors, making the memory controller non-composable. This is addressed by adding a Delay Block to the front-end that delays all signals sent from the front-end to a requestor to always emulate worst-case interference. This makes requestors unable to affect each other’s temporal behavior, which is sufficient to guarantee composability on the level of applications. Our predictable memory controller hence offers composable service with a variety of memory and arbiter types, which widely extends the scope of composable platforms. Another benefit of this approach is that it enables composable service to be dynamically enabled and disabled, enabling requestors that do not require composable service to use slack bandwidth to improve performance. The predictable and composable memory controller is supported by a configuration flow that automatically computes memory patterns and arbiter settings to satisfy given bandwidth and latency requirements. The flow uses abstraction to separate the configuration of the memory and the arbiter, enabling settings to be computed in a streamlined fashion for all supported memories and arbiters

Human-in-the-Loop Model Predictive Control of an Irrigation Canal

Until now, advanced model-based control techniques have been predominantly employed to control problems that are relatively straightforward to model. Many systems with complex dynamics or containing sophisticated sensing and actuation elements can be controlled if the corresponding mathematical models are available, even if there is uncertainty in this information. Consequently, the application of model-based control strategies has flourished in numerous areas, including industrial applications [1]-[3].Junta de Andalucía P11-TEP-812