Self-Evaluation Applied Mathematics 2003-2008 University of Twente

This report contains the self-study for the research assessment of the Department of Applied Mathematics (AM) of the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) at the University of Twente (UT). The report provides the information for the Research Assessment Committee for Applied Mathematics, dealing with mathematical sciences at the three universities of technology in the Netherlands. It describes the state of affairs pertaining to the period 1 January 2003 to 31 December 2008

Explicitly representing the semantics of composite positional tolerance for patterns of holes

Representing the semantics of the interaction of two or more tolerances (i.e. composite tolerance) explicitly to make them computer-understandable is currently a challenging task in computer-aided tolerancing (CAT). We have proposed a description logic (DL) ontology based approach to complete this task recently. In this paper, the representation of the semantics of the composite positional tolerance (CPT) for patterns of holes (POHs) is used as an example to illustrate the proposed approach. This representation mainly includes: representing the structure knowledge of the CPT for POHs in DL terminological axioms; expressing the constraint knowledge with Horn rules; and describing the individual knowledge using DL assertional axioms. By implementing the representation with the web ontology language (OWL) and the semantic web rule language (SWRL), a CPT ontology is developed. This ontology has explicitly computer-understandable semantics due to the logic-based semantics of OWL and SWRL. As is illustrated by an engineering example, such semantics makes it possible to automatically check the consistency, reason out the new knowledge, and implement the semantic interoperability of CPT information. Benefiting from this, the ontology provides a semantic enrichment model for the CPT information extracted from CAD/CAM systems

Custom Integrated Circuits

Contains reports on four research projects.U.S. Air Force - Office of Scientific Research (Contract F49620-81-C-0054)U.S. Air Force - Office of Scientific Research (Contract F49620-84-C-0004)National Science Foundation (Grant ECS81-18160)National Science Foundation (Grant ECS83-10941

Cross-layer system reliability assessment framework for hardware faults

System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.Peer ReviewedPostprint (author's final draft

A Review of Bayesian Methods in Electronic Design Automation

The utilization of Bayesian methods has been widely acknowledged as a viable solution for tackling various challenges in electronic integrated circuit (IC) design under stochastic process variation, including circuit performance modeling, yield/failure rate estimation, and circuit optimization. As the post-Moore era brings about new technologies (such as silicon photonics and quantum circuits), many of the associated issues there are similar to those encountered in electronic IC design and can be addressed using Bayesian methods. Motivated by this observation, we present a comprehensive review of Bayesian methods in electronic design automation (EDA). By doing so, we hope to equip researchers and designers with the ability to apply Bayesian methods in solving stochastic problems in electronic circuits and beyond.Comment: 24 pages, a draft version. We welcome comments and feedback, which can be sent to [email protected]