327 research outputs found
Propuesta de arquitectura y circuitos para la mejora del rango dinámico de sistemas de visión en un chip diseñados en tecnologías CMOS profundamente submicrométrica
El trabajo presentado en esta tesis trata de proponer nuevas técnicas para la expansión
del rango dinámico en sensores electrónicos de imagen. En este caso, hemos dirigido nuestros
estudios hacia la posibilidad de proveer dicha funcionalidad en un solo chip. Esto es, sin
necesitar ningún soporte externo de hardware o software, formando un tipo de sistema
denominado Sistema de Visión en un Chip (VSoC). El rango dinámico de los sensores
electrónicos de imagen se define como el cociente entre la máxima y la mínima iluminación
medible. Para mejorar este factor surgen dos opciones. La primera, reducir la mínima luz
medible mediante la disminución del ruido en el sensor de imagen. La segunda, incrementar la
máxima luz medible mediante la extensión del límite de saturación del sensor.
Cronológicamente, nuestra primera opción para mejorar el rango dinámico se basó en
reducir el ruido. Varias opciones se pueden tomar para mejorar la figura de mérito de ruido del
sistema: reducir el ruido usando una tecnología CIS o usar circuitos dedicados, tales como
calibración o auto cero. Sin embargo, el uso de técnicas de circuitos implica limitaciones, las
cuales sólo pueden ser resueltas mediante el uso de tecnologías no estándar que están
especialmente diseñadas para este propósito. La tecnología CIS utilizada está dirigida a la
mejora de la calidad y las posibilidades del proceso de fotosensado, tales como sensibilidad,
ruido, permitir imagen a color, etcétera. Para estudiar las características de la tecnología en más
detalle, se diseñó un chip de test, lo cual permite extraer las mejores opciones para futuros
píxeles. No obstante, a pesar de un satisfactorio comportamiento general, las medidas referentes
al rango dinámico indicaron que la mejora de este mediante sólo tecnología CIS es muy
limitada. Es decir, la mejora de la corriente oscura del sensor no es suficiente para nuestro
propósito. Para una mayor mejora del rango dinámico se deben incluir circuitos dentro del píxel.
No obstante, las tecnologías CIS usualmente no permiten nada más que transistores NMOS al
lado del fotosensor, lo cual implica una seria restricción en el circuito a usar. Como resultado, el
diseño de un sensor de imagen con mejora del rango dinámico en tecnologías CIS fue
desestimado en favor del uso de una tecnología estándar, la cual da más flexibilidad al diseño
del píxel.
En tecnologías estándar, es posible introducir una alta funcionalidad usando circuitos
dentro del píxel, lo cual permite técnicas avanzadas para extender el límite de saturación de los
sensores de imagen. Para este objetivo surgen dos opciones: adquisición lineal o compresiva. Si
se realiza una adquisición lineal, se generarán una gran cantidad de datos por cada píxel. Como
ejemplo, si el rango dinámico de la escena es de 120dB al menos se necesitarían 20-bits/píxel,
log2(10120/20)=19.93, para la representación binaria de este rango dinámico. Esto necesitaría de
amplios recursos para procesar esta gran cantidad de datos, y un gran ancho de banda para
moverlos al circuito de procesamiento. Para evitar estos problemas, los sensores de imagen de
alto rango dinámico usualmente optan por utilizar una adquisición compresiva de la luz. Por lo
tanto, esto implica dos tareas a realizar: la captura y la compresión de la imagen. La captura de
la imagen se realiza a nivel de píxel, en el dispositivo fotosensor, mientras que la compresión de
la imagen puede ser realizada a nivel de píxel, de sistema, o mediante postprocesado externo.
Usando el postprocesado, existe un campo de investigación que estudia la compresión de
escenas de alto rango dinámico mientras se mantienen los detalles, produciendo un resultado
apropiado para la percepción humana en monitores convencionales de bajo rango dinámico.
Esto se denomina Mapeo de Tonos (Tone Mapping) y usualmente emplea solo 8-bits/píxel para
las representaciones de imágenes, ya que éste es el estándar para las imágenes de bajo rango
dinámico.
Los píxeles de adquisición compresiva, por su parte, realizan una compresión que no es
dependiente de la escena de alto rango dinámico a capturar, lo cual implica una baja compresión
o pérdida de detalles y contraste. Para evitar estas desventajas, en este trabajo, se presenta un
píxel de adquisición compresiva que aplica una técnica de mapeo de tonos que permite la
captura de imágenes ya comprimidas de una forma optimizada para mantener los detalles y el
contraste, produciendo una cantidad muy reducida de datos. Las técnicas de mapeo de tonos
ejecutan normalmente postprocesamiento mediante software en un ordenador sobre imágenes
capturadas sin compresión, las cuales contienen una gran cantidad de datos. Estas técnicas han
pertenecido tradicionalmente al campo de los gráficos por ordenador debido a la gran cantidad
de esfuerzo computacional que requieren. Sin embargo, hemos desarrollado un nuevo algoritmo
de mapeo de tonos especialmente adaptado para aprovechar los circuitos dentro del píxel y que
requiere un reducido esfuerzo de computación fuera de la matriz de píxeles, lo cual permite el
desarrollo de un sistema de visión en un solo chip. El nuevo algoritmo de mapeo de tonos, el
cual es un concepto matemático que puede ser simulado mediante software, se ha implementado
también en un chip. Sin embargo, para esta implementación hardware en un chip son necesarias
algunas adaptaciones y técnicas avanzadas de diseño, que constituyen en sí mismas otra de las
contribuciones de este trabajo. Más aún, debido a la nueva funcionalidad, se han desarrollado
modificaciones de los típicos métodos a usar para la caracterización y captura de imágenes
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Real time occupant detection in high dynamic range environments
The aim of this thesis is to explore strategies for real-time image segmentation of non-rigid objects in a spatio-temporal domain with a stationary camera within an optical high dynamic range environment. Camera, illumination and segmentation techniques are discussed for image processing in environments which are characterized by large intensity fluctuations and hence a high optical dynamic range (HDR), in particular for vehicle interior surveillance.
Since the introduction of the airbag in 1981 numberless lives were saved and bad injuries were avoided. But in recent years the airbag has frequently been in the headlines due to the increasing number of injuries caused by it. To avoid these injuries a new generation of ’smart airbags’ has been designed which shows the ability to inflate in multiple steps and with different volumes. In order to determine the optimal inflation mode for a crash it is necessary to consider information about the interior situation and the occupants of the vehicle. This thesis presents a real-time visual occupant detection and classification system for advanced airbag deployment, utilizing a custom CMOS camera and motion based image segmentation algorithms for embedded systems under adverse illumination conditions.
A novel illumination method is presented which combines a set of images flashed with different radiant intensities, which significantly simplifies image segmentation in HDR environments. With a constant exposure time for the imager a single image can be produced with a compressed dynamic range and a simultaneously reduced offset. This makes it possible to capture a vehicle interior under adverse light conditions without using high dynamic range cameras and without losing image detail. The expansion of this active illumination experiment leads to a novel shadow detection and removal technique that produces a shadow-free scene by simulating an artificial infinite illuminant plane over the held of view. Finally a shadowless image without loss of texture details is obtained without any region extraction phase.
Furthermore, a texture based segmentation approach for stationary cam-eras is presented which is neither effected by sudden illumination changes nor by shadow effects
Matrix Transform Imager Architecture for On-Chip Low-Power Image Processing
Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones
In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image.
The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.Ph.D.Committee Chair: Hasler, Paul; Committee Member: David Anderson; Committee Member: DeWeerth, Steve; Committee Member: Jackson, Joel; Committee Member: Smith, Mar
CMOS SPAD-based image sensor for single photon counting and time of flight imaging
The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised
electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and
temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon
sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology
offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high
sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with
significantly lower cost and comparable performance in low light or high speed scenarios. For example, with
temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be
formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can
yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the
entanglement of photons may be realised.
The goal of this research project is the development of such an image sensor by exploiting single photon
avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology.
SPADs have three key combined advantages over other imaging technologies: single photon sensitivity,
picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue
techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A
SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or
fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that
makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are
captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an
equivalent of 0.06 electrons.
The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast
readout and oversampled image formation are projected towards the formation of binary single photon imagers
or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to
the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error
rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image
sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film.
Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm
precision in a 60cm range
Single-pixel, single-photon three-dimensional imaging
The 3D recovery of a scene is a crucial task with many real-life applications such as self-driving vehicles, X-ray tomography and virtual reality. The recent development of time-resolving detectors sensible to single photons allowed the recovery of the 3D information at high frame rate with unprecedented capabilities. Combined with a timing system, single-photon sensitive detectors
allow the 3D image recovery by measuring the Time-of-Flight (ToF) of the photons scattered back by the scene with a millimetre depth resolution.
Current ToF 3D imaging techniques rely on scanning detection systems or multi-pixel sensor.
Here, we discuss an approach to simplify the hardware complexity of the current 3D imaging ToF techniques using a single-pixel, single-photon sensitive detector and computational imaging algorithms. The 3D imaging approaches discussed in this thesis do not require mechanical moving
parts as in standard Lidar systems. The single-pixel detector allows to reduce the pixel complexity to a single unit and offers several advantages in terms of size, flexibility, wavelength range and cost. The experimental results demonstrate the 3D image recovery of hidden scenes with a subsecond
acquisition time, allowing also non-line-of-sight scenes 3D recovery in real-time. We also introduce the concept of intelligent Lidar, a 3D imaging paradigm based uniquely on the temporal trace of the return photons and a data-driven 3D retrieval algorithm
Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications
This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology
for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD)
PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector.
The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all
operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration.
In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation.
The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches:
• Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research
line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory.
• Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA.
In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership.
The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version
Efficient reconfigurable architectures for 3D medical image compression
This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Recently, the more widespread use of three-dimensional (3-D) imaging modalities,
such as magnetic resonance imaging (MRI), computed tomography (CT), positron
emission tomography (PET), and ultrasound (US) have generated a massive amount
of volumetric data. These have provided an impetus to the development of other
applications, in particular telemedicine and teleradiology. In these fields, medical
image compression is important since both efficient storage and transmission of data
through high-bandwidth digital communication lines are of crucial importance.
Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow
for quick upgradeability with real-time applications. Moreover, in order to obtain
efficient solutions for large medical volumes data, an efficient implementation of
these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system
building block in the construction of high-performance systems at an economical price.
Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent
advantages such as massive parallelism capabilities, multimillion gate counts, and
special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are
optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits
promising results in reducing Gaussian white noise in medical images. In terms of
hardware implementation, promising trade-offs on maximum frequency, throughput
and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC)
has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete
wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that
3-D IT demonstrates better computational complexity than the 3-D DWT, whilst
the 3-D DWT with LS exhibits a lossless compression that is significantly useful for
medical image compression. Additionally, an architecture of CAVLC that is capable
of compressing high-definition (HD) images in real-time without any buffer between
the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the
slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.Ministry of Higher Education Malaysia (MOHE),
Universiti Tun Hussein Onn Malaysia (UTHM) and the British Counci
Large scale reconfigurable analog system design enabled through floating-gate transistors
This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.Ph.D.Committee Chair: Hasler, Paul E.; Committee Member: Anderson, David V.; Committee Member: Ayazi, Farrokh; Committee Member: Degertekin, F. Levent; Committee Member: Hunt, William D
Development of a model for smart card based access control in multi-user, multi-resource, multi-level access systems
The primary focus of this research is an examination of the issues involved in the granting of access in an environment characterised by multiple users, multiple resources and multiple levels of access permission. Increasing levels of complexity in automotive systems provides opportunities for improving the integration and efficiency of the services provided to the operator. The vehicle lease / hire environment provided a basis for evaluating conditional access to distributed, mobile assets where the principal medium for operating in this environment is the Smart Card. The application of Smart Cards to existing vehicle management systems requires control of access to motor vehicles, control of vehicle operating parameters and secure storage of operating information. The issues addressed include examination of the characteristics of the operating environment, development of a model and design, simulation and evaluation of a multiple application Smart Card. The functions provided by the card include identification and authentication, secure hash and encryption functions which may be applied, in general, to a wide range of access problems. Evaluation of the algorithms implemented indicate that the Smart Card design may be provably secure under single use conditions and conditionally secure under multiple use conditions. The simulation of the card design provided data to support further research and shows the design is practical and able to be implemented on current Smart Card types
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