Mathematical Programming Decoding of Binary Linear Codes: Theory and Algorithms

Mathematical programming is a branch of applied mathematics and has recently been used to derive new decoding approaches, challenging established but often heuristic algorithms based on iterative message passing. Concepts from mathematical programming used in the context of decoding include linear, integer, and nonlinear programming, network flows, notions of duality as well as matroid and polyhedral theory. This survey article reviews and categorizes decoding methods based on mathematical programming approaches for binary linear codes over binary-input memoryless symmetric channels.Comment: 17 pages, submitted to the IEEE Transactions on Information Theory. Published July 201

Error control techniques for satellite and space communications

The results included in the Ph.D. dissertation of Dr. Fu Quan Wang, who was supported by the grant as a Research Assistant from January 1989 through December 1992 are discussed. The sections contain a brief summary of the important aspects of this dissertation, which include: (1) erasurefree sequential decoding of trellis codes; (2) probabilistic construction of trellis codes; (3) construction of robustly good trellis codes; and (4) the separability of shaping and coding

Advanced wireless communications using large numbers of transmit antennas and receive nodes

The concept of deploying a large number of antennas at the base station, often called massive multiple-input multiple-output (MIMO), has drawn considerable interest because of its potential ability to revolutionize current wireless communication systems. Most literature on massive MIMO systems assumes time division duplexing (TDD), although frequency division duplexing (FDD) dominates current cellular systems. Due to the large number of transmit antennas at the base station, currently standardized approaches would require a large percentage of the precious downlink and uplink resources in FDD massive MIMO be used for training signal transmissions and channel state information (CSI) feedback. First, we propose practical open-loop and closed-loop training frameworks to reduce the overhead of the downlink training phase. We then discuss efficient CSI quantization techniques using a trellis search. The proposed CSI quantization techniques can be implemented with a complexity that only grows linearly with the number of transmit antennas while the performance is close to the optimal case. We also analyze distributed reception using a large number of geographically separated nodes, a scenario that may become popular with the emergence of the Internet of Things. For distributed reception, we first propose coded distributed diversity to minimize the symbol error probability at the fusion center when the transmitter is equipped with a single antenna. Then we develop efficient receivers at the fusion center using minimal processing overhead at the receive nodes when the transmitter with multiple transmit antennas sends multiple symbols simultaneously using spatial multiplexing

Hardware implementation of a pipelined turbo decoder

Turbo codes have been widely studied since they were first proposed in 1993 by Berrou, Glavieux, and Thitimajshima in "Near Shannon Limit error-correcting coding and decoding: Turbo-codes" [1]. They have the advantage of providing a low bit error rate (BER) in decoding, and outperform linear block and convolutional codes in low signal-to-noise-ratio (SNR) environments. The decoding performance of turbo codes can be very close to the Shannon Limit, about 0.7decibel (dB). It is determined by the architectures of the constituent encoders and interleaver, but is bounded in high SNRs by an error floor. Turbo codes are widely used in communications. We explore the codeword weight spectrum properties that contribute to their excellent performance. Furthermore, the decoding performance is analyzed and compared with the free distance asymptotic performance. A 16-state turbo decoder is implemented using VHSIC Hardware Description Language (VHDL) and then mapped onto a field-programmable gate array (FPGA) board. The hardware implementations are compared with the software simulations to verify the decoding correctness. A pipelined architecture is then implemented which significantly reduces the decoding latency. -- Keywords: turbo codes; decoding performance; Monte Carlo simulations; FPGA implementatio