3,106 research outputs found

    Reliability-aware and energy-efficient system level design for networks-on-chip

    Get PDF
    2015 Spring.Includes bibliographical references.With CMOS technology aggressively scaling into the ultra-deep sub-micron (UDSM) regime and application complexity growing rapidly in recent years, processors today are being driven to integrate multiple cores on a chip. Such chip multiprocessor (CMP) architectures offer unprecedented levels of computing performance for highly parallel emerging applications in the era of digital convergence. However, a major challenge facing the designers of these emerging multicore architectures is the increased likelihood of failure due to the rise in transient, permanent, and intermittent faults caused by a variety of factors that are becoming more and more prevalent with technology scaling. On-chip interconnect architectures are particularly susceptible to faults that can corrupt transmitted data or prevent it from reaching its destination. Reliability concerns in UDSM nodes have in part contributed to the shift from traditional bus-based communication fabrics to network-on-chip (NoC) architectures that provide better scalability, performance, and utilization than buses. In this thesis, to overcome potential faults in NoCs, my research began by exploring fault-tolerant routing algorithms. Under the constraint of deadlock freedom, we make use of the inherent redundancy in NoCs due to multiple paths between packet sources and sinks and propose different fault-tolerant routing schemes to achieve much better fault tolerance capabilities than possible with traditional routing schemes. The proposed schemes also use replication opportunistically to optimize the balance between energy overhead and arrival rate. As 3D integrated circuit (3D-IC) technology with wafer-to-wafer bonding has been recently proposed as a promising candidate for future CMPs, we also propose a fault-tolerant routing scheme for 3D NoCs which outperforms the existing popular routing schemes in terms of energy consumption, performance and reliability. To quantify reliability and provide different levels of intelligent protection, for the first time, we propose the network vulnerability factor (NVF) metric to characterize the vulnerability of NoC components to faults. NVF determines the probabilities that faults in NoC components manifest as errors in the final program output of the CMP system. With NVF aware partial protection for NoC components, almost 50% energy cost can be saved compared to the traditional approach of comprehensively protecting all NoC components. Lastly, we focus on the problem of fault-tolerant NoC design, that involves many NP-hard sub-problems such as core mapping, fault-tolerant routing, and fault-tolerant router configuration. We propose a novel design-time (RESYN) and a hybrid design and runtime (HEFT) synthesis framework to trade-off energy consumption and reliability in the NoC fabric at the system level for CMPs. Together, our research in fault-tolerant NoC routing, reliability modeling, and reliability aware NoC synthesis substantially enhances NoC reliability and energy-efficiency beyond what is possible with traditional approaches and state-of-the-art strategies from prior work

    FOCSI: A new layout regularity metric

    Get PDF
    Technical ReportDigital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce these ICs systematic subwavelength lithography failures. However, there is no metric to evaluate and compare the layout regularity of those regular designs. In this paper we propose a new layout regularity metric called Fixed Origin Corner Square Inspection (FOCSI). FOCSI allows the comparison and quantification of designs in terms of regularity and for any given degree of granularity. When FOCSI is oriented to the evaluation of regularity while applying Lithography Enhancement Techniques, it comprehends layout layers measurements considering the optical interaction length and combines them to obtain the complete layout regularity measure. Examples are provided for 32-bit adders in the 90 nm technology node for the Standard Cell approach and for Via-Configurable Transistor Array regular designs. We show how layouts can be sorted accurately even if their degree of regularity is similar.Preprin

    Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

    Get PDF
    The design of low-power SRAM cell becomes a necessity in today\u27s FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAM-based FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA

    Via-configurable transistors array: a regular design technique to improve ICs yield

    Get PDF
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Our objective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-Ripple Adders from 4 bits to 64 bits.Peer ReviewedPostprint (published version

    Extending the performance of hybrid NoCs beyond the limitations of network heterogeneity

    Get PDF
    To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects (wireline), alternative interconnect fabrics such as inhomogeneous three-dimensional integrated Network-on-Chip (3D NoC) and hybrid wired-wireless Network-on-Chip (WiNoC) have emanated as a cost-effective solution for emerging System-on-Chip (SoC) design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in chip multiprocessor (CMP) demands an on-chip communication infrastructure which can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that, the proposed router can reduce applications’ execution time by an average of 16.9% compared to low-latency routers such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes) the proposed router can improve performance efficiency in terms of average packet delay by an average of 45% (or 50%) in 3D NoCs (or WiNoCs)

    Low Cost Interconnected Architecture for the Hardware Spiking Neural Networks

    Get PDF
    A novel low cost interconnected architecture (LCIA) is proposed in this paper, which is an efficient solution for the neuron interconnections for the hardware spiking neural networks (SNNs). It is based on an all-to-all connection that takes each paired input and output nodes of multi-layer SNNs as the source and destination of connections. The aim is to maintain an efficient routing performance under low hardware overhead. A Networks-on-Chip (NoC) router is proposed as the fundamental component of the LCIA, where an effective scheduler is designed to address the traffic challenge due to irregular spikes. The router can find requests rapidly, make the arbitration decision promptly, and provide equal services to different network traffic requests. Experimental results show that the LCIA can manage the intercommunication of the multi-layer neural networks efficiently and have a low hardware overhead which can maintain the scalability of hardware SNNs

    Coordination of Supply Chain Networks and the Emergence of Mini-maestros

    Get PDF
    Abstract Companies recognize international sourcing as a business practice useful to reduce product prices, deal with supply shortages and identify new competitive suppliers. Effective international sourcing implies the integration and coordination of materials, processes, information flows and multiple producers at each buying location. Many companies do not have the capabilities or the willingness to develop and manage such sourcing networks; therefore, other entities have assumed these responsibilities. These coordinators are in charge of the integration of many suppliers to develop full-package production, serve as liaisons between suppliers’ capabilities and market demands, and provide the technical and financial support to sustain the sourcing network. The review of the industrial clustering and global supply chain literature allowed the identification of such coordinators in Mexico. The emergence and profile of these coordinators is associated with corporate strategies of multinational firms, the efforts of industrial groups, and the governmental policies for the development of dynamic industrial regions. This paper analyzes the characteristics of four coordination models identified in the Mexican context, focusing on their contribution to the participation and upgrading of national suppliers. The profile of the coordinator firm, the type of relations that this firm sustains with producers and the support offered to suppliers is also discussed. A particular emphasis is given to the fourth model where a third party, a knowledge and service company, assumes the coordinator role. The interest on this model is due to its novelty, the flexibility of the sourcing network, and the potential impact on regional development that could result from the intervention of a neutral third party as coordinator of the activities of multiple local and specialized suppliers

    Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip

    Get PDF
    The sustained demand for faster, more powerful chips has been met by the availability of chip manufacturing processes allowing for the integration of increasing numbers of computation units onto a single die. The resulting outcome, especially in the embedded domain, has often been called SYSTEM-ON-CHIP (SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC). MPSoC design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection. With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt. NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable answer to this design concern. By bringing large-scale networking concepts to the on-chip domain, they guarantee a structured answer to present and future communication requirements. The point-to-point connection and packet switching paradigms they involve are also of great help in minimizing wiring overhead and physical routing issues. However, as with any technology of recent inception, NoC design is still an evolving discipline. Several main areas of interest require deep investigation for NoCs to become viable solutions: • The design of the NoC architecture needs to strike the best tradeoff among performance, features and the tight area and power constraints of the onchip domain. • Simulation and verification infrastructure must be put in place to explore, validate and optimize the NoC performance. • NoCs offer a huge design space, thanks to their extreme customizability in terms of topology and architectural parameters. Design tools are needed to prune this space and pick the best solutions. • Even more so given their global, distributed nature, it is essential to evaluate the physical implementation of NoCs to evaluate their suitability for next-generation designs and their area and power costs. This dissertation performs a design space exploration of network-on-chip architectures, in order to point-out the trade-offs associated with the design of each individual network building blocks and with the design of network topology overall. The design space exploration is preceded by a comparative analysis of state-of-the-art interconnect fabrics with themselves and with early networkon- chip prototypes. The ultimate objective is to point out the key advantages that NoC realizations provide with respect to state-of-the-art communication infrastructures and to point out the challenges that lie ahead in order to make this new interconnect technology come true. Among these latter, technologyrelated challenges are emerging that call for dedicated design techniques at all levels of the design hierarchy. In particular, leakage power dissipation, containment of process variations and of their effects. The achievement of the above objectives was enabled by means of a NoC simulation environment for cycleaccurate modelling and simulation and by means of a back-end facility for the study of NoC physical implementation effects. Overall, all the results provided by this work have been validated on actual silicon layout

    Transitioning to a circular business model in sustainable fashion companies

    Get PDF
    The circular economy is a topic of growing interest as it presents an alternative to the current linear model of “take-make-disposal” and is needed to connect the environment and the economic systems. Not only new technologies and collaboration among the supply chain are crucial to achieve the circular economy, but new business models are required to expand the potential and application of circular principles. The fashion industry has an important role in our lives and is responsible for a huge environmental and social impact, what makes it especially interesting for the transition to a circular business model. The objective of this research is to analyze how the adoption of circularity by “born sustainable” fashion companies affect their business model. By identifying and adapting a circular business model framework from the literature to the fashion industry, the aim is to understand how companies from Brazil and Italy implement circular principles in their business models. This study is separated into two papers. The first had the objective of adapting a circular business model framework for fashion apparel manufactures, and experts were interviewed to validate the proposal. The second paper sought to analyze the application of the circular business model framework by four sustainable fashion companies of the aforementioned countries by conducting case studies. Results show that the small sustainable fashion businesses share the concern about the social welfare of the involved in the supply chain and offer garments aiming quality and durability. However, they present different design strategies and differ with respect to the materials used. Besides the design, is part of the implementation of circularity the offer of services such as repair, in which while the ownership is still transferred, increases the interaction with customers. Take-back systems, referring to the collection and management of used garments, are important buy still not widely implemented or utilized, indicating some barriers. Design challenges and high costs due to resources and manual and fairly paid production processes are other common challenges.A economia circular é um tópico de crescente interesse, visto que apresenta uma alternativa ao atual modelo linear de “extrair-produzir-descartar” e é necessária para conectar o meio ambiente e os sistemas econômicos. Não apenas novas tecnologias e colaboração entre a cadeia de suprimentos são cruciais para alcançar uma economia circular, mas novos modelos de negócios são necessários para expandir o potencial e a implementação dos princípios circulares. A indústria da moda tem um papel importante em nossas vidas e é responsável por um enorme impacto ambiental e social, o que a torna especialmente interessante na transição para um modelo de negócios circular. O objetivo desta pesquisa é analisar como a adoção da circularidade por empresas de moda “nascidas sustentáveis” afeta o modelo de negócios. Ao identificar e adaptar um framework de modelo de negócios circular da literatura para a indústria da moda, o objetivo é entender como empresas do Brasil e da Itália implementam princípios circulares em seus modelos de negócios. Este estudo está dividido em dois artigos. O primeiro teve o objetivo de adaptar um framework de modelo de negócios circular para fabricantes de moda, e a proposta foi validada através de entrevistas com especialistas. O segundo artigo procurou analisar a implementação do framework de modelo de negócios circular por quatro empresas de moda sustentável dos países mencionados, através da realização de estudos de caso. Os resultados mostram que pequenas empresas de moda sustentável compartilham a preocupação com o bem-estar social dos participantes da cadeia de suprimentos e oferecem peças e acessórios visando qualidade e durabilidade. No entanto, elas apresentam diferentes estratégias de design e diferem em relação aos materiais utilizados. Além do design, faz parte da implementação da circularidade a oferta de serviços como reparos, onde mesmo com a transferência da propriedade, aumenta a interação da empresa com os clientes. Os sistemas de devolução, referentes à coleta e gerenciamento de roupas e acessórios usados, são importantes embora ainda não amplamente implementados ou utilizados, o que indica algumas barreiras. Desafios de design e altos custos devido a matérias primas, processos de produção manuais e pagamento justo da mão de obra são outros desafios comuns
    corecore