Biology of Applied Digital Ecosystems

A primary motivation for our research in Digital Ecosystems is the desire to exploit the self-organising properties of biological ecosystems. Ecosystems are thought to be robust, scalable architectures that can automatically solve complex, dynamic problems. However, the biological processes that contribute to these properties have not been made explicit in Digital Ecosystems research. Here, we discuss how biological properties contribute to the self-organising features of biological ecosystems, including population dynamics, evolution, a complex dynamic environment, and spatial distributions for generating local interactions. The potential for exploiting these properties in artificial systems is then considered. We suggest that several key features of biological ecosystems have not been fully explored in existing digital ecosystems, and discuss how mimicking these features may assist in developing robust, scalable self-organising architectures. An example architecture, the Digital Ecosystem, is considered in detail. The Digital Ecosystem is then measured experimentally through simulations, with measures originating from theoretical ecology, to confirm its likeness to a biological ecosystem. Including the responsiveness to requests for applications from the user base, as a measure of the 'ecological succession' (development).Comment: 9 pages, 4 figure, conferenc

Exploiting technological synergies for future launch vehicles

Two launch vehicle concepts based on technologies available today or in a short term future in Western Europe are presented. The design of both launchers has the goal of exploiting synergies with current European programs to limit development and operational costs. Technologies of particular interest here are the high performance solid rocket motors with carbon-epoxy filament wound monolithic motor cases and the future high performance cryogenic expander cycle engine Vinci. The first concept dubbed ANGELA (A New GEneration LAuncher) is a study financed with funds of the German Ministry of Economics and managed by the DLR Space Administration. The project, which started in the summer of 2012 aims at designing a low cost versatile launcher able to place payloads between 2 and 5 tons into GTO. Three architectures have been considered during the first phase of the study. This phase was concluded in March 2013 with the preliminary stagings, which will be the starting point of more detailed analyses. The first architecture is made out of an H110 (stage with 110 tons of LOx/LH2) equipped with two Vulcain 2 engines with shortened nozzles and an H29 propelled by a Vinci engine. In addition the variation of the number of P36 solid rocket boosters allow to reach the entire range of payload performance. The second architecture differs from the first one only by the use of a new staged-combustion engine instead of two Vulcain 2 engines. The new engine, which should deliver 1800 kN in vacuum, allows a reduction of the size of the stages to H90-H24, enhanced with P34 boosters. The third and last architecture is a so called Multi PPH. The first stage is a bundle of 2 or 3 P120 solid rocket motors. The second stage is made out of one single P120, strictly similar to those used for the first stage. Finally the upper stage is an H23 equipped with a Vinci engine, the same as the two other architectures. The second launcher concept described in this paper is the small TSTO launch vehicle. It consists of a large solid rocket motor first stage P175 and a cryogenic upper stage propelled by the Vinci engine, H26. The preliminary design performed at DLR-SART considers two target performances. The light version of the small TSTO shall perform Galileo satellite replacement single launch missions to MTO corresponding to a payload performance of about 1400 kg in GTO. A heavy version of the launch vehicle shall be able to launch payloads up to 3000 kg in GTO. The performance increase for the heavy version is made possible by the addition of two pairs of P23 boosters, the second pair being ignited with a delay

Distributed Sensing of Fluid Dynamic Phenomena with the XDense Sensor Grid Network

IEEE International Conference on Cyber Physical Systems, Networks and Applications (CPSNA'15), Hong Kong, China.XDense is a proposed wired mesh grid sensor network system tailored for scenarios that benefit from thousands of sensors per square meter. XDense has scalable network topology and protocols, customizable to application specifics, that enables complex feature extraction in realtime from observed phenomena by exploiting communication and distributed processing capabilities of such network topologies. XDense has been designed with closed-loop CPS applications like active flow control of aircraft wing surfaces in mind. It uses a plug-n-play architecture that allows dimensioning of application specific networks. In this paper, we evaluate the performance of XDense in a fluid dynamic application scenario. With experiments on feature detection and realtime scenarios, we demonstrate the potential of the architecture and discuss practical implementation issues

Thread partitioning and value prediction for exploiting speculative thread-level parallelism

Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model strongly depends on the performance of the control and data speculation techniques. Several hardware-based schemes for partitioning the program into speculative threads are analyzed and evaluated. In general, we find that spawning threads associated to loop iterations is the most effective technique. We also show that value prediction is critical for the performance of all of the spawning policies. Thus, a new value predictor, the increment predictor, is proposed. This predictor is specially oriented for this kind of architecture and clearly outperforms the adapted versions of conventional value predictors such as the last value, the stride, and the context-based, especially for small-sized history tables.Peer ReviewedPostprint (published version

Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories

Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density. A prominent characteristic of DRAM-NVM hybrid memory is that it has NVM access latency much higher than DRAM access latency. We call this inter-memory asymmetry. We observe that parasitic components on a long bitline are a major source of high latency in both DRAM and NVM, and a significant factor contributing to high-voltage operations in NVM, which impact their reliability. We propose an architectural change, where each long bitline in DRAM and NVM is split into two segments by an isolation transistor. One segment can be accessed with lower latency and operating voltage than the other. By introducing tiers, we enable non-uniform accesses within each memory type (which we call intra-memory asymmetry), leading to performance and reliability trade-offs in DRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, we exploit both inter- and intra-memory asymmetries to allocate and migrate memory pages between the tiers in DRAM and NVM. Second, we improve the OS's page allocation decisions by predicting the access intensity of a newly-referenced memory page in a program and placing it to a matching tier during its initial allocation. This minimizes page migrations during program execution, lowering the performance overhead. Third, we propose a solution to migrate pages between the tiers of the same memory without transferring data over the memory channel, minimizing channel occupancy and improving performance. Our overall approach, which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybrid tiered memory improves both performance and reliability for both single-core and multi-programmed workloads.Comment: 15 pages, 29 figures, accepted at ACM SIGPLAN International Symposium on Memory Managemen