A survey of dynamic power optimization techniques

One of the most important considerations for the current VLSI/SOC design is power, which can be classified into power analysis and optimization. In this survey, the main concepts of power optimization including the sources and policies are introduced. Among the various approaches, dynamic power management (DPM), which implies to change devices states when they are not working at the highest speed or at their full capacity, is the most efficient one. Our explanations accompanying the figures specify the abstract concepts of DPM. This paper briefly surveys both heuristic and stochastic policies and discusses their advantages and disadvantages

Lifetime-aware cloud data centers: models and performance evaluation

We present a model to evaluate the server lifetime in cloud data centers (DCs). In particular, when the server power level is decreased, the failure rate tends to be reduced as a consequence of the limited number of components powered on. However, the variation between the different power states triggers a failure rate increase. We therefore consider these two effects in a server lifetime model, subject to an energy-aware management policy. We then evaluate our model in a realistic case study. Our results show that the impact on the server lifetime is far from negligible. As a consequence, we argue that a lifetime-aware approach should be pursued to decide how and when to apply a power state change to a server

Performance analysis of pre-equalized multilevel partial response schemes

In order to achieve high speed on electrical interconnects, channel attenuation at high frequencies must be dealt with by proper transceiver design. In this paper we investigate finite-complexity MMSE pre-equalization under an average transmit power constraint, to compensate for channel distortion in the case of both full-response and precoded partial response signaling with L-PAM mapping, and consider the resulting error performance for symbol-by-symbol detection and sequence detection. For a representative electrical interconnect, we point out that the constellation size (2-PAM or 4-PAM), the type of signaling (full response or partial response), the detection method (symbol-by-symbol detection or sequence detection) and the number of pre-equalizer taps should be carefully selected in order to achieve satisfactory error performance at high data rates. For several scenarios, precoded duobinary 4-PAM is found to yield the best error performance for given average transmit power

Custom Integrated Circuits

Contains reports on twelve research projects.Analog Devices, Inc.International Business Machines, Inc.Joint Services Electronics Program (Contract DAAL03-86-K-0002)Joint Services Electronics Program (Contract DAAL03-89-C-0001)U.S. Air Force - Office of Scientific Research (Grant AFOSR 86-0164)Rockwell International CorporationOKI Semiconductor, Inc.U.S. Navy - Office of Naval Research (Contract N00014-81-K-0742)Charles Stark Draper LaboratoryNational Science Foundation (Grant MIP 84-07285)National Science Foundation (Grant MIP 87-14969)Battelle LaboratoriesNational Science Foundation (Grant MIP 88-14612)DuPont CorporationDefense Advanced Research Projects Agency/U.S. Navy - Office of Naval Research (Contract N00014-87-K-0825)American Telephone and TelegraphDigital Equipment CorporationNational Science Foundation (Grant MIP-88-58764