189 research outputs found
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Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of hardware Trojans inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart from the threats in various forms, some of the embedded security applications such as random number generators (RNGs) suffer from the impacts of process variations and noise in nanometer CMOS. Despite their disadvantages, the random and unique nature of process variations can be exploited for generating unique identifiers and can be of tremendous use in embedded security.
In this dissertation, we explore techniques for precise fault-injection in cryptographic hardware based on voltage/temperature manipulation and hardware Trojan insertion. We demonstrate the effectiveness of these techniques by mounting fault attacks on state-of-the-art ciphers. Physically Unclonable Functions (PUFs) are novel cryptographic primitives for extracting secret keys from complex manufacturing variations in integrated circuits (ICs). We explore the vulnerabilities of some of the popular strong PUF architectures to modeling attacks using Machine Learning (ML) algorithms. The attacks use silicon data from a test chip manufactured in IBM 32nm silicon-on-insulator (SOI) technology. Attack results demonstrate that the majority of strong PUF architectures can be predicted to very high accuracies using limited training data. We also explore the techniques to exploit unreliable data from strong PUF architectures and effectively use them to improve the prediction accuracies of modeling attacks. Motivated by the vulnerabilities of existing PUF architectures, we present a novel modeling attack resistant PUF architecture based on non-linear computing elements. Post-silicon validation results are used to demonstrate the effectiveness of the non-linear PUF architecture against modeling and fault-injection attacks. Apart from the techniques to improve the security of PUF circuits, we also present novel solutions to improve the performance of PUF circuits from the perspectives of IC fabrication and system/protocol design. Finally, we present a statistical benchmark suite to evaluate PUFs in conceptualization phase and also to enable fine-grained security assessments for varying PUF parameters. Data compressibility analyses for validating the statistical benchmark suite are also presented
Hardware Trojan Detection Using Controlled Circuit Aging
This paper reports a novel approach that uses transistor aging in an
integrated circuit (IC) to detect hardware Trojans. When a transistor is aged,
it results in delays along several paths of the IC. This increase in delay
results in timing violations that reveal as timing errors at the output of the
IC during its operation. We present experiments using aging-aware standard cell
libraries to illustrate the usefulness of the technique in detecting hardware
Trojans. Combining IC aging with over-clocking produces a pattern of bit errors
at the IC output by the induced timing violations. We use machine learning to
learn the bit error distribution at the output of a clean IC. We differentiate
the divergence in the pattern of bit errors because of a Trojan in the IC from
this baseline distribution. We simulate the golden IC and show robustness to
IC-to-IC manufacturing variations. The approach is effective and can detect a
Trojan even if we place it far off the critical paths. Results on benchmarks
from the Trust-hub show a detection accuracy of 99%.Comment: 21 pages, 34 figure
Logic Locking based Trojans: A Friend Turns Foe
Logic locking and hardware Trojans are two fields in hardware security that
have been mostly developed independently from each other. In this paper, we
identify the relationship between these two fields. We find that a common
structure that exists in many logic locking techniques has desirable properties
of hardware Trojans (HWT). We then construct a novel type of HWT, called
Trojans based on Logic Locking (TroLL), in a way that can evade
state-of-the-art ATPG-based HWT detection techniques. In an effort to detect
TroLL, we propose customization of existing state-of-the-art ATPG-based HWT
detection approaches as well as adapting the SAT-based attacks on logic locking
to HWT detection. In our experiments, we use random sampling as reference. It
is shown that the customized ATPG-based approaches are the best performing but
only offer limited improvement over random sampling. Moreover, their efficacy
also diminishes as TroLL's triggers become longer, i.e., have more bits
specified). We thereby highlight the need to find a scalable HWT detection
approach for TroLL.Comment: 9 pages, double column, 8 figures, IEEE forma
DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans
The global semiconductor supply chain involves design and fabrication at
various locations, which leads to multiple security vulnerabilities, e.g.,
Hardware Trojan (HT) insertion. Although most HTs target digital circuits, HTs
can be inserted in analog circuits. Therefore, several techniques have been
developed for HT insertions in analog circuits. Capacitance-based Analog
Hardware Trojan (AHT) is one of the stealthiest HT that can bypass most
existing HT detection techniques because it uses negligible charge accumulation
in the capacitor to generate stealthy triggers. To address the charge sharing
and accumulation issues, we propose a novel way to detect such
capacitance-based AHT in this paper. Secondly, we critically analyzed existing
AHTs to highlight their respective limitations. We proposed a stealthier
capacitor-based AHT (fortified AHT) that can bypass our novel AHT detection
technique by addressing these limitations. Finally, by critically analyzing the
proposed fortified AHT and existing AHTs, we developed a robust two-phase
framework (DeMiST) in which a synchronous system can mitigate the effects of
capacitance-based stealthy AHTs by turning off the triggering capability of
AHT. In the first phase, we demonstrate how the synchronous system can avoid
the AHT during run-time by controlling the supply voltage of the intermediate
combinational circuits. In the second phase, we proposed a supply voltage duty
cycle-based validation technique to detect capacitance-based AHTs. Furthermore,
DeMiST amplified the switching activity for charge accumulation to such a
degree that it can be easily detectable using existing switching activity-based
HT detection techniques.Comment: Accepted at ACM Hardware and Architectural Support for Security and
Privacy (HASP) 202
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