1,990 research outputs found

    Reliability and Security Assessment of Modern Embedded Devices

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    L'abstract è presente nell'allegato / the abstract is in the attachmen

    A Comprehensive Survey on Non-Invasive Fault Injection Attacks

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    Non-invasive fault injection attacks have emerged as significant threats to a spectrum of microelectronic systems ranging from commodity devices to high-end customized processors. Unlike their invasive counterparts, these attacks are more affordable and can exploit system vulnerabilities without altering the hardware physically. Furthermore, certain non-invasive fault injection strategies allow for remote vulnerability exploitation without the requirement of physical proximity. However, existing studies lack extensive investigation into these attacks across diverse target platforms, threat models, emerging attack strategies, assessment frameworks, and mitigation approaches. In this paper, we provide a comprehensive overview of contemporary research on non-invasive fault injection attacks. Our objective is to consolidate and scrutinize the various techniques, methodologies, target systems susceptible to the attacks, and existing mitigation mechanisms advanced by the research community. Besides, we categorize attack strategies based on several aspects, present a detailed comparison among the categories, and highlight research challenges with future direction. By underlining and discussing the landscape of cutting-edge, non-invasive fault injection, we hope more researchers, designers, and security professionals examine the attacks further and take such threats into consideration while developing effective countermeasures

    New Techniques for On-line Testing and Fault Mitigation in GPUs

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    L'abstract è presente nell'allegato / the abstract is in the attachmen

    Fault-tolerant protection of near-term trapped-ion topological qubits under realistic noise sources

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    The quest of demonstrating beneficial quantum error correction in near-term noisy quantum processors can benefit enormously from a low-resource optimization of fault-tolerant schemes, which are specially designed for a particular platform considering both state-of-the-art technological capabilities and main sources of noise. In this work, we show that flag-qubit-based fault-tolerant techniques for active error detection and correction, as well as for encoding of logical qubits, can be leveraged in current designs of trapped-ion quantum processors to achieve this break-even point of beneficial quantum error correction. Our improved description of the relevant sources of noise, together with detailed schedules for the implementation of these flag-based protocols, provide one of the most complete microscopic characterizations of a fault-tolerant quantum processor to date. By extensive numerical simulations, we provide a comparative study of flag- and cat-based approaches to quantum error correction, and show that the superior performance of the former can become a landmark in the success of near-term quantum computing with noisy trapped-ion devices.Comment: new version, accepted in Phys. Rev.

    Remote Attacks on FPGA Hardware

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    Immer mehr Computersysteme sind weltweit miteinander verbunden und über das Internet zugänglich, was auch die Sicherheitsanforderungen an diese erhöht. Eine neuere Technologie, die zunehmend als Rechenbeschleuniger sowohl für eingebettete Systeme als auch in der Cloud verwendet wird, sind Field-Programmable Gate Arrays (FPGAs). Sie sind sehr flexible Mikrochips, die per Software konfiguriert und programmiert werden können, um beliebige digitale Schaltungen zu implementieren. Wie auch andere integrierte Schaltkreise basieren FPGAs auf modernen Halbleitertechnologien, die von Fertigungstoleranzen und verschiedenen Laufzeitschwankungen betroffen sind. Es ist bereits bekannt, dass diese Variationen die Zuverlässigkeit eines Systems beeinflussen, aber ihre Auswirkungen auf die Sicherheit wurden nicht umfassend untersucht. Diese Doktorarbeit befasst sich mit einem Querschnitt dieser Themen: Sicherheitsprobleme die dadurch entstehen wenn FPGAs von mehreren Benutzern benutzt werden, oder über das Internet zugänglich sind, in Kombination mit physikalischen Schwankungen in modernen Halbleitertechnologien. Der erste Beitrag in dieser Arbeit identifiziert transiente Spannungsschwankungen als eine der stärksten Auswirkungen auf die FPGA-Leistung und analysiert experimentell wie sich verschiedene Arbeitslasten des FPGAs darauf auswirken. In der restlichen Arbeit werden dann die Auswirkungen dieser Spannungsschwankungen auf die Sicherheit untersucht. Die Arbeit zeigt, dass verschiedene Angriffe möglich sind, von denen früher angenommen wurde, dass sie physischen Zugriff auf den Chip und die Verwendung spezieller und teurer Test- und Messgeräte erfordern. Dies zeigt, dass bekannte Isolationsmaßnahmen innerhalb FPGAs von böswilligen Benutzern umgangen werden können, um andere Benutzer im selben FPGA oder sogar das gesamte System anzugreifen. Unter Verwendung von Schaltkreisen zur Beeinflussung der Spannung innerhalb eines FPGAs zeigt diese Arbeit aktive Angriffe, die Fehler (Faults) in anderen Teilen des Systems verursachen können. Auf diese Weise sind Denial-of-Service Angriffe möglich, als auch Fault-Angriffe um geheime Schlüsselinformationen aus dem System zu extrahieren. Darüber hinaus werden passive Angriffe gezeigt, die indirekt die Spannungsschwankungen auf dem Chip messen. Diese Messungen reichen aus, um geheime Schlüsselinformationen durch Power Analysis Seitenkanalangriffe zu extrahieren. In einer weiteren Eskalationsstufe können sich diese Angriffe auch auf andere Chips auswirken die an dasselbe Netzteil angeschlossen sind wie der FPGA. Um zu beweisen, dass vergleichbare Angriffe nicht nur innerhalb FPGAs möglich sind, wird gezeigt, dass auch kleine IoT-Geräte anfällig für Angriffe sind welche die gemeinsame Spannungsversorgung innerhalb eines Chips ausnutzen. Insgesamt zeigt diese Arbeit, dass grundlegende physikalische Variationen in integrierten Schaltkreisen die Sicherheit eines gesamten Systems untergraben können, selbst wenn der Angreifer keinen direkten Zugriff auf das Gerät hat. Für FPGAs in ihrer aktuellen Form müssen diese Probleme zuerst gelöst werden, bevor man sie mit mehreren Benutzern oder mit Zugriff von Drittanbietern sicher verwenden kann. In Veröffentlichungen die nicht Teil dieser Arbeit sind wurden bereits einige erste Gegenmaßnahmen untersucht

    Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements

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    Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear to which extend fault injection can provide an accurate error rate estimation at early stages and if beam experiments can be used to identify the weakest resources in a device. The importance and challenges associated with a timely, but yet realistic reliability evaluation grow with the increase of complexity in both the hardware domain, with the integration of different types of cores in an SoC (System-on-Chip), and the software domain, with the OS (operating system) required to take full advantage of the available resources. In this paper, we combine and analyze data gathered with extensive beam experiments (on the final physical CPU hardware) and microarchitectural fault injections (on early microarchitectural CPU models). We target a standalone Arm Cortex-A5 CPU and an Arm Cortex-A9 CPU integrated into an SoC and evaluate their reliability in bare-metal and Linux-based configurations. Combining experimental data that covers more than 18 million years of device time with the result of more than 176,000 injections we find that both the SoC integration and the presence of the OS increase the system DUEs (Detected Unrecoverable Errors) rate (for different reasons) but do not significantly impact the SDCs (Silent Data Corruptions) rate which is solely attributed to the CPU core. Our reliability analysis demonstrates that even considering SoC integration and OS inclusion, early, pre-silicon microarchitecture-level fault injection delivers accurate SDC rates estimations and lower bounds for the DUE rates

    Developing a distributed electronic health-record store for India

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    The DIGHT project is addressing the problem of building a scalable and highly available information store for the Electronic Health Records (EHRs) of the over one billion citizens of India

    Review of selection criteria for sensor and actuator configurations suitable for internal combustion engines

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    This literature review considers the problem of finding a suitable configuration of sensors and actuators for the control of an internal combustion engine. It takes a look at the methods, algorithms, processes, metrics, applications, research groups and patents relevant for this topic. Several formal metric have been proposed, but practical use remains limited. Maximal information criteria are theoretically optimal for selecting sensors, but hard to apply to a system as complex and nonlinear as an engine. Thus, we reviewed methods applied to neighboring fields including nonlinear systems and non-minimal phase systems. Furthermore, the closed loop nature of control means that information is not the only consideration, and speed, stability and robustness have to be considered. The optimal use of sensor information also requires the use of models, observers, state estimators or virtual sensors, and practical acceptance of these remains limited. Simple control metrics such as conditioning number are popular, mostly because they need fewer assumptions than closed-loop metrics, which require a full plant, disturbance and goal model. Overall, no clear consensus can be found on the choice of metrics to define optimal control configurations, with physical measures, linear algebra metrics and modern control metrics all being used. Genetic algorithms and multi-criterial optimisation were identified as the most widely used methods for optimal sensor selection, although addressing the dimensionality and complexity of formulating the problem remains a challenge. This review does present a number of different successful approaches for specific applications domains, some of which may be applicable to diesel engines and other automotive applications. For a thorough treatment, non-linear dynamics and uncertainties need to be considered together, which requires sophisticated (non-Gaussian) stochastic models to establish the value of a control architecture

    System data communication structures for active-control transport aircraft, volume 2

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    The application of communication structures to advanced transport aircraft are addressed. First, a set of avionic functional requirements is established, and a baseline set of avionics equipment is defined that will meet the requirements. Three alternative configurations for this equipment are then identified that represent the evolution toward more dispersed systems. Candidate communication structures are proposed for each system configuration, and these are compared using trade off analyses; these analyses emphasize reliability but also address complexity. Multiplex buses are recognized as the likely near term choice with mesh networks being desirable for advanced, highly dispersed systems
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