Switchable Imbibition in Nanoporous Gold

Spontaneous imbibition enables the elegant propelling of nano-flows because of the dominance of capillarity at small length scales. The imbibition kinetics are, however, solely determined by the static geometry of the porous host, the capillarity, and the fluidity of the imbibed liquid. This makes active control particularly challenging. Here, we show for aqueous electrolyte imbibition in nanoporous gold that the fluid flow can be reversibly switched on and off through electric potential control of the solid-liquid interfacial tension, i.e. we can accelerate the imbibition front, stop it, and have it proceed at will. Simultaneous measurements of the mass flux and the electrical current allow us to document simple scaling laws for the imbibition kinetics, and to explore the charge flow dynamics in the metallic nanopores. Our findings demonstrate that the high electric conductivity along with the pathways for ionic and/or fluid transport render nanoporous elemental gold a versatile, accurately controllable electro-capillary pump and flow sensor for minute amounts of liquids with exceptionally low operating voltages.Comment: 12 pages, 5 figure

Soil moisture and heat budget evaluation in selected European zones of agricultural and environmental interest

There are no author-identified significant results in this report

Source-tracking cadmium in New Zealand agricultural soils: a stable isotope approach

Cadmium (Cd) is a toxic heavy metal, which is accumulated by plants and animals and therefore enters the human food chain. In New Zealand (NZ), where Cd mainly originates from the application of phosphate fertilisers, stable isotopes can be used to trace the fate of Cd in soils and potentially the wider environment due to the limited number of sources in this setting. Prior to 1997, extraneous Cd added to soils in P fertilisers was essentially limited to a single source, the small pacific island of Nauru. Analysis of Cd isotope ratios (ɛ114/110Cd) in Nauru rock phosphate, pre-1997 superphosphate fertilisers, and Canterbury (Lismore Stony Silt Loam) topsoils (Winchmore Research Farm) has demonstrated their close similarity with respect to ɛ114/110Cd. We report a consistent ɛ114/110Cd signature in fertiliser-derived Cd throughout the latter twentieth century. This finding is useful because it allows the application of mixing models to determine the proportions of fertiliser-derived Cd in the wider environment. We believe this approach has good potential because we also found the ɛ114/110Cd in fertilisers to be distinct from unfertilised Canterbury subsoils. In our analysis of the Winchmore topsoil series (1949-2015), the ɛ114/110Cd remained quite constant following the change from Nauru to other rock phosphate sources in 1997, despite a corresponding shift in fertiliser ɛ114/110Cd at this time. We can conclude that to the present day, the Cd in topsoil at Winchmore still mainly originates from historical phosphate fertilisers. One implication of this finding is that the current applications of P fertiliser are not resulting in further Cd accumulation. We aim to continue our research into Cd fate, mobility and transformations in the NZ environment by applying Cd isotopes in soils and aquatic environments across the country

QoS-aware mechanisms for improving cost-efficiency of datacenters

Warehouse Scale Computers (WSCs) promise high cost-efficiency by amortizing power, cooling, and management overheads. WSCs today host a large variety of jobs with two broad performance requirements categories: latency-critical (LC) and best-effort (BE). Ideally, to fully utilize all hardware resources, WSC operators can simply fill all the nodes with computing jobs. Unfortunately, because colocated jobs contend for shared resources, systems with high loads often experience performance degradation, which negatively impacts the Quality of Service (QoS) for LC jobs. In fact, service providers usually over-provision resources to avoid any interference with LC jobs, leading to significant resource inefficiencies. In this dissertation, I explore opportunities across different system-abstraction layers to improve the cost-efficiency of dataceters by increasing resource utilization of WSCs with little or no impact on the performance of LC jobs. The dissertation has three main components. First, I explore opportunities to improve the throughput of multicore systems by reducing the performance variation of LC jobs. The main insight is that by reshaping the latency distribution curve, performance headroom of LC jobs can be effectively converted to improved BE throughput. I develop, implement, and evaluate a runtime system that achieves this goal with existing hardware. I leverage the cache partitioning, per-core frequency scaling, and thread masking of server processors. Evaluation results show the proposed solution enables 30% higher system throughput compared to solutions proposed in prior works while maintaining at least as good QoS for LC jobs. Second, I study resource contention in near-future heterogeneous memory architectures (HMA). This study is motivated by recent developments in non-volatile memory (NVM) technologies, which enable higher storage density at the cost of same performance. To understand the performance and QoS impact of HMAs, I design and implement a performance emulator in the Linux kernel that runs unmodified workloads with high accuracy, low overhead, and complete transparency. I further propose and evaluate multiple data and resource management QoS mechanisms, such as locality-aware page admission, occupancy management, and write buffer jailing. Third, I focus on accelerated machine learning (ML) systems. By profiling the performance of production workloads and accelerators, I show that accelerated ML tasks are highly sensitive to main memory interference due to fine-grained interaction between CPU and accelerator tasks. As a result, memory resource contention can significantly decreases the performance and efficiency gains of accelerators. I propose a runtime system that leverages existing hardware capabilities and show 17% higher system efficiency compared to previous approaches. This study further exposes opportunities for future processor architecturesElectrical and Computer Engineerin

Conceptual Design of an In-Space Cryogenic Fluid Management Facility

The conceptual design of a Spacelab experiment to develop the technology associated with low gravity propellant management is presented. The proposed facility consisting of a supply tank, receiver tank, pressurization system, instrumentation, and supporting hardware, is described. The experimental objectives, the receiver tank to be modeled, and constraints imposed on the design by the space shuttle, Spacelab, and scaling requirements, are described. The conceptual design, including the general configurations, flow schematics, insulation systems, instrumentation requirements, and internal tank configurations for the supply tank and the receiver tank, is described. Thermal, structural, fluid, and safety and reliability aspects of the facility are analyzed. The facility development plan, including schedule and cost estimates for the facility, is presented. A program work breakdown structure and master program schedule for a seven year program are included

Annual Report: 2009

I submit herewith the annual report from the Agricultural and Forestry Experiment Station, School of Natural Resources and Agricultural Sciences, University of Alaska Fairbanks, for the period ending December 31, 2009. This is done in accordance with an act of Congress, approved March 2, 1887, entitled, “An act to establish agricultural experiment stations, in connection with the agricultural college established in the several states under the provisions of an act approved July 2, 1862, and under the acts supplementary thereto,” and also of the act of the Alaska Territorial Legislature, approved March 12, 1935, accepting the provisions of the act of Congress. The research reports are organized according to our strategic plan, which focuses on high-latitude soils, high-latitude agriculture, natural resources use and allocation, ecosystems management, and geographic information. These areas cross department and unit lines, linking them and unifying the research. We have also included in our financial statement information on the special grants we receive. These special grants allow us to provide research and outreach that is targeted toward economic development in Alaska. Research conducted by our graduate and undergraduate students plays an important role in these grants and the impact they make on Alaska.Financial statement -- Grants -- Students -- Research Reports: Partners, Facilities, and Programs; Geography; High-Latitude Agriculture; High-Latitude Soils; Management of Ecosystems; Natural Resources Use and Allocation; Index to Reports -- Publications -- Facult

Design and development of deadline based scheduling mechanisms for multiprocessor systems

Multiprocessor systems are nowadays de facto standard for both personal computers and server workstations. Benefits of multicore technology will be used in the next few years for embedded devices and cellular phones as well. Linux, as a General Purpose Operating System (GPOS), must support many different hardware platform, from workstations to mobile devices. Unfortu- nately, Linux has not been designed to be a Real-Time Operating System (RTOS). As a consequence, time-sensitive (e.g. audio/video players) or sim- ply real-time interactive applications, may suffer degradations in their QoS. In this thesis we extend the implementation of the “Earliest Deadline First” algorithm in the Linux kernel from single processor to multicore systems, allowing processes migration among the CPUs. We also discuss the design choices and present the experimental results that show the potential of our work

Plasma Edge Kinetic-MHD Modeling in Tokamaks Using Kepler Workflow for Code Coupling, Data Management and Visualization

A new predictive computer simulation tool targeting the development of the H-mode pedestal at the plasma edge in tokamaks and the triggering and dynamics of edge localized modes (ELMs) is presented in this report. This tool brings together, in a coordinated and effective manner, several first-principles physics simulation codes, stability analysis packages, and data processing and visualization tools. A Kepler workflow is used in order to carry out an edge plasma simulation that loosely couples the kinetic code, XGC0, with an ideal MHD linear stability analysis code, ELITE, and an extended MHD initial value code such as M3D or NIMROD. XGC0 includes the neoclassical ion-electron-neutral dynamics needed to simulate pedestal growth near the separatrix. The Kepler workflow processes the XGC0 simulation results into simple images that can be selected and displayed via the Dashboard, a monitoring tool implemented in AJAX allowing the scientist to track computational resources, examine running and archived jobs, and view key physics data, all within a standard Web browser. The XGC0 simulation is monitored for the conditions needed to trigger an ELM crash by periodically assessing the edge plasma pressure and current density profiles using the ELITE code. If an ELM crash is triggered, the Kepler workflow launches the M3D code on a moderate-size Opteron cluster to simulate the nonlinear ELM crash and to compute the relaxation of plasma profiles after the crash. This process is monitored through periodic outputs of plasma fluid quantities that are automatically visualized with AVS/Express and may be displayed on the Dashboard. Finally, the Kepler workflow archives all data outputs and processed images using HPSS, as well as provenance information about the software and hardware used to create the simulation. The complete process of preparing, executing and monitoring a coupled-code simulation of the edge pressure pedestal buildup and the ELM cycle using the Kepler scientific workflow system is described in this paper

서비스 균등 분배와 고성능을 위한 다중프로세서칩 상의 재구성형 통신 구조

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 최기영.The chip multiprocessor (CMP) era has long begun due to the diminishing return from instruction-level parallelism (ILP) harvesting techniques, the rising power and temperature from frequency scaling, etc. One powerful processor has been replaced by many less-powerful processors forming a CMP. One of the issues arose from this paradigm shift is the management of communication among the processors. Buses, which has been a common choice for the systems with one or several processors, failed to sustain the increased communication burden of CMPs. Many bus-based improvements including hierarchical buses and bus-matrices, were proposed but eventually, network-on-chip (NoC) has become the de facto standard for designing a CMP system, replacing the bus-based techniques. NoCs strengths over bus mainly come from its capability of conveying multiple transactions simultaneously from different components to the others. The concurrent communications between the cores are conducted by the distributed, yet shared network components, routers. Routers provide cores with services such as bandwidths. One of the design issues in implementing NoC is to distribute these services evenly across all the cores requesting for them. Arbiter is a component that regulates the accesses to shared resources such as channels and buffers. It has the policy under which requests get services in turn from the shared resources so that the requestors dont fall into deadlock or starvation. One of the common policies for an arbiter is the round-robin, where requests get their grant one by one so that fairness is assured among the requestors. When applied to routers in NoC, it fails to provide the fairness because each request goes through multiple routers, thus multiple round-robin arbiters on a transaction route. The cascaded effect of the round-robin arbitration is that the farther a source is from the destination, the less service it gets from the destination. The first part of this thesis addresses this issue, and proposes thus far the simplest yet the most effective way of providing the fairness to all the nodes on NoC. It applies weighted round-robin scheme where the weights are determined at run-time depending on which cores are allocated to applications or threads running on the CMP. RTL implementation and synthesis are done to show the simplicity of the proposed scheme. Simulation with synthetic traffic patterns and SPEC CPU2006 benchmark applications show that the proposed approach results in outstanding equality-of-service characteristics. The second part of this thesis deals with the impact of the reconfigurable communication architecture on the performance of a CMP system. One of the pitfalls of NoC is long access latency due to increased hop count between a source and its destination. For example, NoC with mesh topology has its hop count proportional to its size. Because of this, while being a common choice for CMP, mesh topology is said to be inscalable in terms of the number of cores. Some alternatives to mesh topology exist, one of them being high radix NoCs. They replace short and wide channels of mesh with long and narrow ones achieving fewer hop counts. Another option is to cluster cores so that the dimension of mesh network reduces. The clusters are formed by grouping cores via local communication fabric. The clusters are interconnected by a global communication fabric, often in the shape of mesh topology. Many types of local communication fabric are explored in previous researches, including another NoC with topologies of mesh, ring, etc. However, bus has become one of the most favorable choices for the local connection because of its simplicity. The simplicity leads local communications to be performed with high performance, low chip area, low power consumption, etc. One of the issues in forming core clusters in CMP is their grain size. Tying too many cores into a cluster results in the congestion on the bus, reducing the performance of the local communications. On the other hand, too few cores in a cluster misses the chances of improving system performance by efficient local communications through the bus. It is obvious that the optimal number of cores in a cluster depends on the applications that run on the CMP. Bus reconfiguration with bus segments and switches can be a solution for varying cluster size on a CMP. In addition to the variable cluster sizes, bus reconfiguration has another advantage of processor (not process) migration. Bus reconfiguration can reconnect cores and caches so that the distance between cores and data are reduced dynamically. In this way, data copies and network transactions can be dramatically reduced to improve the system performance. The second part of this thesis addresses this issue and proposes a reconfigurable bus-mesh architecture to accelerate pipelined applications. With the proposed architecture, the data transfer between the successive pipeline stages are done not by data copies but by processor migrations. Systematic management of bus segments and L1 data caches are required to achieve efficient use of the reconfigurability. The proposed architecture is compared with the baseline architecture, which maintains cache coherence with hardware. Multilayer perceptron (MLP), convolutional neural network (CNN), and JPEG decoder are implemented as example pipelined applications using multi-threaded programming model. The in-house full system simulator is implemented and used to measure the performance improvement of the proposed architecture. The experimental results show that 21.75 %, 14.40 %, and 12.74 % execution cycle reductions are achieved for MLP, CNN, and JPEG decoder, respectively.Part I Adaptively Weighted Round-Robin Arbitration for Equality of Service in a Many-Core Network-on-Chip [1] 1 Chapter 1 Introduction 3 Chapter 2 Previous Work 7 Chapter 3 Position-Based Weighted Round-Robin Arbitration 11 Chapter 4 Adaptively Weighted Round-Robin Arbitration 17 4.1 Hardware Implementation for weight update 18 4.2 Arbitration Weight Determination 22 Chapter 5 Experimental Results 25 5.1 Open-Loop Measurements 25 5.2 Closed-Loop Measurements 29 5.3 Hardware Implementation 33 Chapter 6 Conclusion 35 Part II Accelerating Pipelined Applications with Reconfigurable Bus-Mesh Communication Architecture in Chip Multiprocessors 37 Chapter 7 Introduction 39 Chapter 8 Backgrounds and Previous Work 43 8.1 Segmented Bus 43 8.2 CMPs with Reconfigurable Bus-Mesh Communication Architecture 44 8.3 Near-Threshold Computing 48 Chapter 9 Baseline Architecture 51 Chapter 10 Motivation 55 Chapter 11 Reconfigurable Bus-Mesh Architecture 61 11.1 Thread Programming Model 61 11.2 Cluster Size 64 11.3 Organizing Multiple L1Ds and SPM Banks in a Cluster 66 11.4 L1 Data Cache / SPM Partitioning 70 11.5 Reconfiguration Overheads 71 Chapter 12 Experimental Results 75 12.1 Pipelined Applications 75 12.2 Simulation Environment 78 12.3 Memory Operations Latency Breakdown 79 Chapter 13 Conclusion 85 Bibliography 87 국문초록 95Docto