DYNAMIC RANGE LIMITATIONS OF LOW-NOISE MICROWAVE TRANSISTORS AT CRYOGENIC TEMPERATURES

Dynamic range is an important metric that specifies the limits of input signal amplitude for the ideal operation of a given receiver. The low end of dynamic range is defined by the noise floor whereas the upper limit is determined by large-signal distortion. While dynamic range can be predicted in the temperature range where compact transistor models are valid, the lack of large-signal models at temperatures below -55 C prevents the prediction and optimization of dynamic range for applications that require cryogenic cooling. For decades, the main goal concerning the performance of these applications was lowering the noise floor of cryogenic receiver front-ends. For this, linear small-signal noise models have been extensively studied and used for designs of low-noise amplifiers. In this work, the existing small-signal noise modeling approach is extended to capture the weakly nonlinear properties of the transistors that are commonly used in cryogenic amplification. Indium phosphide high electron mobility transistors and silicon germanium heterojunction bipolar transistors are considered. The goal of this work is to identify the fundamental dynamic range limitations of these transistors such that the results are not device specific, but applicable to the corresponding device families. Identifying the fundamental limitations of dynamic range in a semiconductor device requires a broad understanding of physical properties of the transistors. For this, a theoretical analysis will be presented first as a function of temperature. The small-signal noise modeling will then be discussed using techniques that are well recognized in the literature. This will be followed by an explanation of the nonlinear modeling approach used in this work. This approach relies on the definition of Taylor series expansion coefficients of the dominant nonlinear mechanisms of the transistors. The modeling results will be interpreted with respect to the initially presented theoretical framework. Finally, the dynamic range performance will be studied as a function of source and load terminations. In addition to this systematic approach to understanding the physical limitations of dynamic range, model to measurement agreement of broadband cryogenic amplifiers will also be presented which will verify the accuracy of the modeling approach

High-Power Comb-Line Filter Architectures for Switched-Mode RF Power Amplifier Systems

Die vorgelegte Arbeit behandelt die Analyse der Anforderungen, denschaltungstechnischen Entwurf, den Aufbau und die messtechnische Verifizierungvon Rekonstruktionsfiltern für Leistungsschaltverstärker im Klasse-SBetrieb, die auf Grund ihres hohen Wirkungsgrades vorzugsweise in MobilfunkbasisstationenVerwendung finden sollen. Die Brauchbarkeit des Entwurfeswird an Hand einer Reihe von Applikationsbeispielen anschaulich dargestellt.Als Kernforderung einer derartigen Filterauslegung hat sich die Aufrechterhaltungder Rechteckzeitfunktion des Drain-Stromes für einen (im ”CurrentMode” arbeitenden) Schaltverstärker herausgestellt, weil sonst die damit erzielbarehohe Effizienz nicht erreicht werden kann. Darüber hinaus fließen indie Filterauslegung nicht nur die Fixierung des Filterdurchlass- und sperrbereichesein, sondern auch die Festlegung der Eingangs- und Lastimpedanz bei unterschiedlichenAnregungsmoden über einen breiten Frequenzbereich. Doppelundeinzelterminierte Filter werden theoretisch betrachtet, simuliert, getestetund gemessen.Es wurde herausgearbeitet, dass die schaltungstechnischen und geometrischenAnforderungen an einen derartigen Rekonstruktionsfilterentwurf gutdurch symmetrisch gespeiste Kammleitungsfilter erfüllt werden können. VerschiedeneFilterarchitekturen werden im Hinblick auf ihr Gleich- und Gegentaktaktimpedanzverhaltenvorgestellt, experimentell untersucht und kritischanalysiert. Soweit dem Autor bekannt ist, werden hier erstmalig Rekonstruktionsfilterfür Klasse-S Leistungsverstärker im ”Current Mode” komplett analysiert.Desweiteren wird die Funktionalität des Rekonstruktionsfilters an Handanderer Typen von Leistungsschaltverstärkern simuliert und messtechnisch untersucht.Der maximale Wirkungsgrad von 65% bei Leistungsschaltverstärkersystemenlässt sich dem erfolgreichen Filterentwurf zuschreiben.This work has taken place in the context that a class-S power amplifiersystem with simplified transmitter architectures and increased power efficiencymakes an attractive candidate for cellular phone base transceiver station applications.The author describes the requirements for, and a number of successfulimplementations of, a reconstruction filter suitable for such an amplifier system.In a current-mode class-S power amplifier system, crucial to the maintenanceof the rectangular shape of the drain current and thus to high efficiency arenot only the tailoring of pass-band and stop-band, but also the specification ofinput impedance for different modes of excitation over a wide frequency range.Doubly and singly terminated filters are subjected to theoretical consideration,simulation, testing and measurement. The main focus of the research is on thedesign of the reconstruction filter.It is found that the electrical and geometrical constraints for the designof a reconstruction filter are well satisfied by balanced input comb-line filters.Several filter architectures are proposed, experimentally investigated, and criticallyanalysed in terms of differential and common mode impedances. Thisis the first complete analysis of reconstruction filters for current mode class-Spower amplifier systems, as far as the author knows. Switched-mode poweramplifier systems which include the proposed filters are also simulated andmeasured under different driving conditions. The maximum power efficiencyof 65% to date in the switched-mode power amplifier systems can be attributedto the successful filter design

Integrated RF oscillators and LO signal generation circuits

This thesis deals with fully integrated LC oscillators and local oscillator (LO) signal generation circuits. In communication systems a good-quality LO signal for up- and down-conversion in transmitters is needed. The LO signal needs to span the required frequency range and have good frequency stability and low phase noise. Furthermore, most modern systems require accurate quadrature (IQ) LO signals. This thesis tackles these challenges by presenting a detailed study of LC oscillators, monolithic elements for good-quality LC resonators, and circuits for IQ-signal generation and for frequency conversion, as well as many experimental circuits. Monolithic coils and variable capacitors are essential, and this thesis deals with good structures of these devices and their proper modeling. As experimental test devices, over forty monolithic inductors and thirty varactors have been implemented, measured and modeled. Actively synthesized reactive elements were studied as replacements for these passive devices. At first glance these circuits show promising characteristics, but closer noise and nonlinearity analysis reveals that these circuits suffer from high noise levels and a small dynamic range. Nine circuit implementations with various actively synthesized variable capacitors were done. Quadrature signal generation can be performed with three different methods, and these are analyzed in the thesis. Frequency conversion circuits are used for alleviating coupling problems or to expand the number of frequency bands covered. The thesis includes an analysis of single-sideband mixing, frequency dividers, and frequency multipliers, which are used to perform the four basic arithmetical operations for the frequency tone. Two design cases are presented. The first one is a single-sideband mixing method for the generation of WiMedia UWB LO-signals, and the second one is a frequency conversion unit for a digital period synthesizer. The last part of the thesis presents five research projects. In the first one a temperature-compensated GaAs MESFET VCO was developed. The second one deals with circuit and device development for an experimental-level BiCMOS process. A cable-modem RF tuner IC using a SiGe process was developed in the third project, and a CMOS flip-chip VCO module in the fourth one. Finally, two frequency synthesizers for UWB radios are presented

Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

Journal of Telecommunications and Information Technology, 2003, nr 1

kwartalni

Application of waveform engineering to GaN HFET characterisation and class F design

In this work, the largely theoretical existing research on class F has been extended to include a measured waveform based analysis. The results demonstrate how optimum class F performance can be achieved using real devices and highlights a number of interesting issues that a designer of a class F amplifier should consider.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields