Expansion of layouts of complete binary trees into grids

AbstractLet Th be the complete binary tree of height h. Let M be the infinite grid graph with vertex set Z2, where two vertices (x1,y1) and (x2,y2) of M are adjacent if and only if |x1−x2|+|y1−y2|=1. Suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of M. Motivated by issues in optimal VLSI design, we show that the point expansion ratio n(T)/n(Th)=n(T)/(2h+1−1) is bounded below by 1.122 for h sufficiently large. That is, we give bounds on how many vertices of degree 2 must be inserted along the edges of Th in order that the resulting tree can be laid out in the grid. Concerning the constructive end of VLSI design, suppose that T is a tree which is a subdivision of Th and is also isomorphic to a subgraph of the n×n grid graph. Define the expansion ratio of such a layout to be n2/n(Th)=n2/(2h+1−1). We show constructively that the minimum possible expansion ratio over all layouts of Th is bounded above by 1.4656 for sufficiently large h. That is, we give efficient layouts of complete binary trees into square grids, making improvements upon the previous work of others. We also give bounds for the point expansion and expansion problems for layouts of Th into extended grids, i.e. grids with added diagonals

Complexity dichotomy on partial grid recognition

Deciding whether a graph can be embedded in a grid using only unit-length edges is NP-complete, even when restricted to binary trees. However, it is not difficult to devise a number of graph classes for which the problem is polynomial, even trivial. A natural step, outstanding thus far, was to provide a broad classification of graphs that make for polynomial or NP-complete instances. We provide such a classification based on the set of allowed vertex degrees in the input graphs, yielding a full dichotomy on the complexity of the problem. As byproducts, the previous NP-completeness result for binary trees was strengthened to strictly binary trees, and the three-dimensional version of the problem was for the first time proven to be NP-complete. Our results were made possible by introducing the concepts of consistent orientations and robust gadgets, and by showing how the former allows NP-completeness proofs by local replacement even in the absence of the latter

Placement techniques in automatic analog layout generation.

模擬電路版圖設計是一個非常複雜和耗時的過程。通常情況下，設計一個高質量的模擬電路版圖需要電子工程師花費幾週甚至更長的時間。模擬電路的電子特性對於電路的細節設計非常敏感，因此，減小電路中的失配現象成為模擬電路版圖設計中一個非常重要的課題。在本論文中，我們提出了一系列實際的佈局技術，來降低電路的失配並提高繞線的成功率。我們可以非常容易的將這些技術整合至一個完整的模擬佈局和佈線的工具中，此工具可以在幾分鐘內生成一個完整的、高質量的模擬電路版圖。同時，該版圖能夠通過設計規則驗證（DRC）和佈局與電路設計一致性檢測（LVS）。模擬結果顯示，它的電路性能能夠與達到甚至超出手工設計的電路版圖。我們的論文主要作出了以下兩方面貢獻。1. 平衡佈局：對於模擬電路中的電子元器件，如電容、電阻、晶體管等進行一維和二維的平衡佈局。電子工程師可以根據不同的設計需求，通過選擇不同的佈局參數來改變電路的佈局排列方式。同時，在模擬退火算法中，我們著重考慮了器件間的匹配以生成高質量的模擬電路佈局。2. 消除阻塞的電路佈局：在模擬電路設計中，我們期望盡量避免在電子元器件密度較高的區域進行繞線。因此，我們需要在電路佈局設計過程中在電子元器件間留有足夠的佈線空間。為達到這個目標，我們提出了更精確的阻塞估計方法和版圖拓展方法，使其能夠生成一個高質量、高繞線成功率的電路佈局結果。為了驗證生成的電路版圖的質量和匹配特性，我們利用蒙地卡羅方法來模擬電路中的製程偏差和失配特性。實驗結果顯示，我們的工具可以在幾分鐘內自動生成高質量的電路版圖，與人工設計通常需要花費數日至數週相比，設計時間大幅縮短，同時電路的匹配特性得以提升。Analog layout design is a complicated and time-consuming process. It often takes couples of weeks for the layout designers to generate a qualied layout. The elec-trical properties of analog circuit are very sensitive to the layout details, and mis-match reduction becomes a very important issue in analog layout design.In this thesis, we will present some practical placement techniques to reduce mismatch and improve routability. These techniques can be easily integrated into a complete analog placement and routing ow, which can produce in just a few min-utes a complete and high quality layout for analog circuits that passes the design rule check, layout-schematic check and with performance veried by simulations. The contents of this thesis will focus on the following two issues:(1) Symmetry Placement: We consider symmetric placement of transistors, re-sistors and capacitors, which includes 1-D symmetry and 2-D symmetry (or called common centroid). Different symmetric placement congurations, derived accord-ing to the practical needs in analog design, are considered for the matching devices in the simulated annealing engine of the placer in order to generate a placement with high quality.(2) Congestion-driven Placement: In analog design, wires are preferred not be routed over active devices, so we need to leave enough spaces properly for routing between the devices during the placement process. To achieve this, we explore congestion estimation and layout expansion during the placement step in order to produce a good and routable solution.In order to verify the quality of the generated layouts in terms of mismatch, we will run Monte Carlo simulations on them with variations in process and mismatch. Experiments show that our methodology can generate high quality layout automatically in just a few minutes while manual design may take couples of days.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Detailed summary in vernacular field only.Cui, Guxin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.Abstracts also in Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Physical Design --- p.2Chapter 1.3 --- Analog Placement --- p.4Chapter 1.3.1 --- Methodologies of Analog Placement --- p.4Chapter 1.3.2 --- Symmetry Constraints of Analog Placement --- p.5Chapter 1.4 --- Process Variation and Layout Mismatch --- p.6Chapter 1.4.1 --- Process Variation --- p.6Chapter 1.4.2 --- Random Mismatch and Systematic Mismatch --- p.7Chapter 1.5 --- Monte Carlo Simulation Procedure --- p.9Chapter 1.6 --- Problem Formulation of Placement --- p.9Chapter 1.7 --- Motivations --- p.10Chapter 1.8 --- Contributions --- p.11Chapter 1.9 --- Thesis Organization --- p.12Chapter 2 --- Literature Review on Analog Placement --- p.13Chapter 2.1 --- Topological Representations Handling Symmetry Constraints --- p.14Chapter 2.1.1 --- Symmetry within the Sequence-Pair (SP) Representation . --- p.14Chapter 2.1.2 --- Block Placement with Symmetry Constraints Based on the O-Tree Non-Slicing Representation --- p.16Chapter 2.1.3 --- Placement with Symmetry Constraints for Analog Layout Design Using TCG-S --- p.17Chapter 2.1.4 --- Modeling Non-Slicing Floorplans with Binary Trees --- p.19Chapter 2.1.5 --- Segment Trees Handle Symmetry Constraints --- p.20Chapter 2.1.6 --- Center-based Corner Block List --- p.22Chapter 2.2 --- Other Works on Analog Placement Constraints --- p.25Chapter 2.2.1 --- Deterministic Analog Placement with Hierarchically Bounded Enumeration and Enhanced Shape Functions --- p.25Chapter 2.2.2 --- Analog Placement Based on Symmetry-Island Formulation --- p.27Chapter 2.2.3 --- Heterogeneous B*-Trees for Analog Placement with Symmetry and Regularity Considerations --- p.28Chapter 2.3 --- Summary --- p.31Chapter 3 --- Common-Centroid Analog Placement --- p.32Chapter 3.1 --- Problem Formulation --- p.33Chapter 3.2 --- Overview of Our Work --- p.35Chapter 3.3 --- Handling Common Centroid Constraints in Different Devices --- p.37Chapter 3.3.1 --- Common Centroid Placement of Resistors --- p.38Chapter 3.3.2 --- Common Centroid Placement of Transistors --- p.44Chapter 3.3.3 --- Common Centroid Placement of Capacitors --- p.47Chapter 3.4 --- Congestion Estimation and Layout Expansion --- p.50Chapter 3.4.1 --- Blockage-Aware Congestion Estimation --- p.51Chapter 3.4.2 --- Layout Expansion --- p.56Chapter 3.5 --- Simulated Annealing --- p.59Chapter 3.5.1 --- Types of Moves --- p.59Chapter 3.5.2 --- Handling Devices in Symmetry Group --- p.59Chapter 3.5.3 --- Cost Function of Simulated Annealing --- p.61Chapter 3.6 --- Summary --- p.62Chapter 4 --- Experimental Results and Monte-Carlo Simulations --- p.64Chapter 4.1 --- Study of Congestion-driven Layout Expansion --- p.64Chapter 4.2 --- Monte Carlo Simulations --- p.70Chapter 4.2.1 --- Devices Modeling --- p.70Chapter 4.2.2 --- Study of Layouts with and without Symmetry Groups --- p.71Chapter 4.2.3 --- Study of Layouts with and without Self-Symmetry Devices --- p.73Chapter 4.2.4 --- Study of Layouts with Different Number of Symmetry Groups --- p.74Chapter 4.2.5 --- Study of Large and Small Size Capacitors Array --- p.76Chapter 4.3 --- Comparison of Automatic and Manual Layouts using Monte Carlo Simulations --- p.79Chapter 5 --- Conclusion --- p.86Bibliography --- p.8

Using genetic algorithms to find cellular automata rule sets capable of generating maze-like game level layouts

The video game industry has grown substantially over the last decade and the quality of video games has also been advancing rapidly. In recent years, video games have been advancing to a point that the increased time required to manually create their content is making this process too costly. This has made procedural content generation a desirable option for game developers due to its speed of generating content, and the variety of content that a single PCG method can produced. The main purpose of this dissertation is to detail a new approach to procedurally generate video game level layouts, and to aid in further research in the area of procedural video game content generation. The new PCG approach investigated and developed in this study combined a genetic algorithm with cellular automata and a maze generation technique into a method for generating game level layouts with desired maze-like properties. The GA in this approach was utilized to evolve CA rules that, when applied to a maze configuration, would produce layouts with desired properties. This research discovered that CA rules could be evolved to generate level layouts with desired properties, and that there were a number of parameters which could affect the layouts these rules produced. These parameters include the number of cell states used in the CA, as well as the CA’s neighbourhood size and the number of times the CA rules were applied to their maze configurations. This research also discovered that the one factor that had the largest impact on the visual aspect of the generated layouts was the chosen chromosome representation

Practical Techniques for Improving Performance and Evaluating Security on Circuit Designs

As the modern semiconductor technology approaches to nanometer era, integrated circuits (ICs) are facing more and more challenges in meeting performance demand and security. With the expansion of markets in mobile and consumer electronics, the increasing demands require much faster delivery of reliable and secure IC products. In order to improve the performance and evaluate the security of emerging circuits, we present three practical techniques on approximate computing, split manufacturing and analog layout automation. Approximate computing is a promising approach for low-power IC design. Although a few accuracy-configurable adder (ACA) designs have been developed in the past, these designs tend to incur large area overheads as they rely on either redundant computing or complicated carry prediction. We investigate a simple ACA design that contains no redundancy or error detection/correction circuitry and uses very simple carry prediction. The simulation results show that our design dominates the latest previous work on accuracy-delay-power tradeoff while using 39% less area. One variant of this design provides finer-grained and larger tunability than that of the previous works. Moreover, we propose a delay-adaptive self-configuration technique to further improve the accuracy-delay-power tradeoff. Split manufacturing prevents attacks from an untrusted foundry. The untrusted foundry has front-end-of-line (FEOL) layout and the original circuit netlist and attempts to identify critical components on the layout for Trojan insertion. Although defense methods for this scenario have been developed, the corresponding attack technique is not well explored. Hence, the defense methods are mostly evaluated with the k-security metric without actual attacks. We develop a new attack technique based on structural pattern matching. Experimental comparison with existing attack shows that the new attack technique achieves about the same success rate with much faster speed for cases without the k-security defense, and has a much better success rate at the same runtime for cases with the k-security defense. The results offer an alternative and practical interpretation for k-security in split manufacturing. Analog layout automation is still far behind its digital counterpart. We develop the layout automation framework for analog/mixed-signal ICs. A hierarchical layout synthesis flow which works in bottom-up manner is presented. To ensure the qualified layouts for better circuit performance, we use the constraint-driven placement and routing methodology which employs the expert knowledge via design constraints. The constraint-driven placement uses simulated annealing process to find the optimal solution. The packing represented by sequence pairs and constraint graphs can simultaneously handle different kinds of placement constraints. The constraint-driven routing consists of two stages, integer linear programming (ILP) based global routing and sequential detailed routing. The experiment results demonstrate that our flow can handle complicated hierarchical designs with multiple design constraints. Furthermore, the placement performance can be further improved by using mixed-size block placement which works on large blocks in priority