Realizing live sequence charts in SystemVerilog.

The design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, live sequence charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications

Mining Branching-Time Scenarios

Specification mining extracts candidate specification from existing systems, to be used for downstream tasks such as testing and verification. Specifically, we are interested in the extraction of behavior models from execution traces

Synthesis and distribution of modal transition systems from triggered scenarios

Synthesis of operational behaviour models from scenario-based specifications has been extensively studied. Focus has been mainly on either existential or universal interpretations. Existing model synthesis techniques use traditional two-valued behaviour models such as Labeled Transition Systems (LTS). We propose a scenario-based language that supports both existential and universal interpretations for conditional scenarios. We show that LTS are not sufficiently expressive to accommodate such languages and shift the target of synthesis to Modal Transition Systems (MTS), an extension of LTS that can distinguish between required, unknown and proscribed behaviour to capture the semantics of existential and universal scenarios. MTSs support elaboration of behaviour models through refinement, which complements an incremental elicitation process suitable for specifying behaviour with scenario-based notations. The synthesis algorithm that we define constructs an MTS that uses refinement to characterise all the LTS models that satisfy a mixed, conditional existential and universal scenario-based specification. In order to capture all permissible implementations, model MTSs of component based systems are given at the system level. However, iterative refinement by engineers is often more convenient at the component level. We address the problem of decomposing partial behaviour models from a single monolithic model to a component model. We prove that a sound and complete distribution can be built when the MTS to be distributed is deterministic, transition modalities are consistent and the LTS determined by its possible transitions is distributable. We show how this combination of scenario language, synthesis, MTSs, and distribution supports behaviour model elaboration.Open Acces