Using ant colony optimization for routing in microprocesors

Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers

An Ultra-Low-Energy, Variation-Tolerant FPGA Architecture Using Component-Specific Mapping

As feature sizes scale toward atomic limits, parameter variation continues to increase, leading to increased margins in both delay and energy. Parameter variation both slows down devices and causes devices to fail. For applications that require high performance, the possibility of very slow devices on critical paths forces designers to reduce clock speed in order to meet timing. For an important and emerging class of applications that target energy-minimal operation at the cost of delay, the impact of variation-induced defects at very low voltages mandates the sizing up of transistors and operation at higher voltages to maintain functionality. With post-fabrication configurability, FPGAs have the opportunity to self-measure the impact of variation, determining the speed and functionality of each individual resource. Given that information, a delay-aware router can use slow devices on non-critical paths, fast devices on critical paths, and avoid known defects. By mapping each component individually and customizing designs to a component's unique physical characteristics, we demonstrate that we can eliminate delay margins and reduce energy margins caused by variation. To quantify the potential benefit we might gain from component-specific mapping, we first measure the margins associated with parameter variation, and then focus primarily on the energy benefits of FPGA delay-aware routing over a wide range of predictive technologies (45 nm--12 nm) for the Toronto20 benchmark set. We show that relative to delay-oblivious routing, delay-aware routing without any significant optimizations can reduce minimum energy/operation by 1.72x at 22 nm. We demonstrate how to construct an FPGA architecture specifically tailored to further increase the minimum energy savings of component-specific mapping by using the following techniques: power gating, gate sizing, interconnect sparing, and LUT remapping. With all optimizations considered we show a minimum energy/operation savings of 2.66x at 22 nm, or 1.68--2.95x when considered across 45--12 nm. As there are many challenges to measuring resource delays and mapping per chip, we discuss methods that may make component-specific mapping more practical. We demonstrate that a simpler, defect-aware routing achieves 70% of the energy savings of delay-aware routing. Finally, we show that without variation tolerance, scaling from 16 nm to 12 nm results in a net increase in minimum energy/operation; component-specific mapping, however, can extend minimum energy/operation scaling to 12 nm and possibly beyond.</p

SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator

Spatial processing of sparse, irregular floating-point computation using a single FPGA enables up to an order of magnitude speedup (mean 2.8X speedup) over a conventional microprocessor for the SPICE circuit simulator. We deliver this speedup using a hybrid parallel architecture that spatially implements the heterogeneous forms of parallelism available in SPICE. We decompose SPICE into its three constituent phases: Model-Evaluation, Sparse Matrix-Solve, and Iteration Control and parallelize each phase independently. We exploit data-parallel device evaluations in the Model-Evaluation phase, sparse dataflow parallelism in the Sparse Matrix-Solve phase and compose the complete design in streaming fashion. We name our parallel architecture SPICE²: Spatial Processors Interconnected for Concurrent Execution for accelerating the SPICE circuit simulator. We program the parallel architecture with a high-level, domain-specific framework that identifies, exposes and exploits parallelism available in the SPICE circuit simulator. This design is optimized with an auto-tuner that can scale the design to use larger FPGA capacities without expert intervention and can even target other parallel architectures with the assistance of automated code-generation. This FPGA architecture is able to outperform conventional processors due to a combination of factors including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and overlapped processing of the control algorithms. We demonstrate that we can independently accelerate Model-Evaluation by a mean factor of 6.5X(1.4--23X) across a range of non-linear device models and Matrix-Solve by 2.4X(0.6--13X) across various benchmark matrices while delivering a mean combined speedup of 2.8X(0.2--11X) for the two together when comparing a Xilinx Virtex-6 LX760 (40nm) with an Intel Core i7 965 (45nm). With our high-level framework, we can also accelerate Single-Precision Model-Evaluation on NVIDIA GPUs, ATI GPUs, IBM Cell, and Sun Niagara 2 architectures. We expect approaches based on exploiting spatial parallelism to become important as frequency scaling slows down and modern processing architectures turn to parallelism (\eg multi-core, GPUs) due to constraints of power consumption. This thesis shows how to express, exploit and optimize spatial parallelism for an important class of problems that are challenging to parallelize.</p

Neural Activity During Audiovisual Speech Processing: Protocol For a Functional Neuroimaging Study.

BACKGROUND The field of health information management (HIM) focuses on the protection and management of health information from a variety of sources. The American Health Information Management Association (AHIMA) Council for Excellence in Education (CEE) determines the needed skills and competencies for this field. AHIMA's HIM curricula competencies are divided into several domains among the associate, undergraduate, and graduate levels. Moreover, AHIMA's career map displays career paths for HIM professionals. What is not known is whether these competencies and the career map align with industry demands. OBJECTIVE The primary aim of this study is to analyze HIM job postings on a US national job recruiting website to determine whether the job postings align with recognized HIM domains, while the secondary aim is to evaluate the AHIMA career map to determine whether it aligns with the job postings. METHODS A national job recruitment website was mined electronically (web scraping) using the search term "health information management." This cross-sectional inquiry evaluated job advertisements during a 2-week period in 2021. After the exclusion criteria, 691 job postings were analyzed. Data were evaluated with descriptive statistics and natural language processing (NLP). Soft cosine measures (SCM) were used to determine correlations between job postings and the AHIMA career map, curricular competencies, and curricular considerations. ANOVA was used to determine statistical significance. RESULTS Of all the job postings, 29% (140/691) were in the Southeast, followed by the Midwest (140/691, 20%), West (131/691,19%), Northeast (94/691, 14%), and Southwest (73/691, 11%). The educational levels requested were evenly distributed between high school diploma (219/691, 31.7%), associate degree (269/691, 38.6%), or bachelor's degree (225/691, 32.5%). A master's degree was requested in only 8% (52/691) of the postings, with 72% (42/58) preferring one and 28% (16/58) requiring one. A Registered Health Information Technologist (RHIT) credential was the most commonly requested (207/691, 29.9%) in job postings, followed by Registered Health Information Administrator (RHIA; 180/691, 26%) credential. SCM scores were significantly higher in the informatics category compared to the coding and revenue cycle (P=.006) and data analytics categories (P<.001) but not significantly different from the information governance category (P=.85). The coding and revenue cycle category had a significantly higher SCM score compared to the data analytics category (P<.001). Additionally, the information governance category was significantly higher than the data analytics category (P<.001). SCM scores were significantly different between each competency category, except there were no differences in the average SCM score between the information protection and revenue cycle management categories (P=.96) and the information protection and data structure, content, and information governance categories (P=.31). CONCLUSIONS Industry job postings primarily sought a high school diploma and associate degrees, with a master's degree a distant third. NLP analysis of job postings suggested that the correlation between the informatics category and job postings was higher than that of the coding, revenue cycle, and data analytics categories. INTERNATIONAL REGISTERED REPORT IDENTIFIER (IRRID) DERR1-10.2196/38407