5,412 research outputs found
A Combined Gate Replacement and Input Vector Control Approach
Due to the increasing role of leakage power in CMOS circuit's total power dissipation, leakage reduction has attracted a lot of attention recently. Input vector control (IVC) takes advantage of the transistor stack effect to apply the minimum leakage vector (MLV) to the primary inputs of the circuit during the standby mode. However, IVC techniques become less effective for circuits of large logic depth because theMLV at primary inputs has little impact on internal gates at high logic level.
In this paper, we propose a technique to overcome this limitation by directly controlling the inputs to the internal gates that are in their worst leakage states. Specifically, we propose a gate replacement technique that replaces such gates by other library gates while maintaining the circuit's correct functionality at the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction, when the MLV is not effective. We then describe a divideand- conquer approach that combines the gate replacement and input vector control techniques. It integrates an algorithm that finds the optimal MLV for tree circuits, a fast gate replacement heuristic, and a genetic algorithm that connects the tree circuits.
We have conducted experiments on all the MCNC91 benchmark circuits. The results reveal that 1) the gate replacement technique itself can provide 10% more leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; 3) when we obtain the optimal MLV for small circuits from exhaustive search, the proposed gate replacement alone can still reduce leakage current by 13% while the divide-and-conquer approach reduces 17%
Leakage Minimization Technique for Nanoscale CMOS VLSI
Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents
Accurate Macro-Modeling for Leakage Current for I\u3csub\u3eDDQ\u3c/sub\u3e Test
This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results
Computing leakage current distributions and determination of minimum leakage vectors for combinational designs
Analyzing circuit leakage and minimizing leakage during the standby mode of oper-
ation of a circuit are important problems faced during contemporary circuit design.
Analysis of the leakage profiles of an implementation would enable a designer to
select between several implementations in a leakage optimal way. Once such an im-
plementation is selected, minimizing leakage during standby operation (by finding
the minimum leakage state over all input vector states) allows further power reduc-
tions. However, both these problems are NP-hard. Since leakage power is currently
approaching about half the total circuit power, these two problems are of prime rel-
evance.
This thesis addresses these NP-hard problems. An Algebraic Decision Diagram
(ADD) based approach to determine and implicitly represent the leakage value for all
input vectors of a combinational circuit is presented. In its exact form, this technique
can compute the leakage value of each input vector, by storing these leakage values
implicitly in an ADD structure. To broaden the applicability of this technique, an
approximate version of the algorithm is presented as well. The approximation is done
by limiting the total number of discriminant nodes in any ADD. It is experimentally
demonstrated that these approximate techniques produce results with quantifiable
errors. In particular, it is shown that limiting the number of discriminants to a value between 12 and 16 is practical, allowing for good accuracy and lowered memory
utilization.
In addition, a heuristic approach to determine the input vector which minimizes
leakage for a combinational design is presented. Approximate signal probabilities of
internal nodes are used as a guide in finding the minimum leakage vector. Probabilistic
heuristics are used to select the next gate to be processed, as well as to select the
best state of the selected gate. A fast satisfiability solver is employed to ensure the
consistency of the assignments that are made in this process. Experimental results
indicate that this method has very low run-times, with excellent accuracy, compared
to existing approaches
An efficient null space inexact Newton method for hydraulic simulation of water distribution networks
Null space Newton algorithms are efficient in solving the nonlinear equations
arising in hydraulic analysis of water distribution networks. In this article,
we propose and evaluate an inexact Newton method that relies on partial updates
of the network pipes' frictional headloss computations to solve the linear
systems more efficiently and with numerical reliability. The update set
parameters are studied to propose appropriate values. Different null space
basis generation schemes are analysed to choose methods for sparse and
well-conditioned null space bases resulting in a smaller update set. The Newton
steps are computed in the null space by solving sparse, symmetric positive
definite systems with sparse Cholesky factorizations. By using the constant
structure of the null space system matrices, a single symbolic factorization in
the Cholesky decomposition is used multiple times, reducing the computational
cost of linear solves. The algorithms and analyses are validated using medium
to large-scale water network models.Comment: 15 pages, 9 figures, Preprint extension of Abraham and Stoianov, 2015
(https://dx.doi.org/10.1061/(ASCE)HY.1943-7900.0001089), September 2015.
Includes extended exposition, additional case studies and new simulations and
analysi
The Cryogenic Target for the G Experiment at Jefferson Lab
A cryogenic horizontal single loop target has been designed, built, tested
and operated for the G experiment in Hall C at Jefferson Lab. The target
cell is 20 cm long, the loop volume is 6.5 l and the target operates with the
cryogenic pump fully immersed in the fluid. The target has been designed to
operate at 30 Hz rotational pump speed with either liquid hydrogen or liquid
deuterium. The high power heat exchanger is able to remove 1000 W of heat from
the liquid hydrogen, while the nominal electron beam with current of 40 A
and energy of 3 GeV deposits about 320 W of heat into the liquid. The increase
in the systematic uncertainty due to the liquid hydrogen target is negligible
on the scale of a parity violation experiment. The global normalized yield
reduction for 40 A beam is about 1.5 % and the target density fluctuations
contribute less than 238 ppm (parts per million) to the total asymmetry width,
typically about 1200 ppm, in a Q bin.Comment: 27 pages, 14 figure
A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction
Input vector control (IVC) is a popular technique for
leakage power reduction. It utilizes the transistor stack effect in
CMOS gates by applying a minimum leakage vector (MLV) to the
primary inputs of combinational circuits during the standby mode.
However, the IVC technique becomes less effective for circuits of
large logic depth because the input vector at primary inputs has
little impact on leakage of internal gates at high logic levels. In this
paper, we propose a technique to overcome this limitation by replacing
those internal gates in their worst leakage states by other
library gates while maintaining the circuit’s correct functionality
during the active mode. This modification of the circuit does not require
changes of the design flow, but it opens the door for further
leakage reduction when the MLV is not effective. We then present
a divide-and-conquer approach that integrates gate replacement,
an optimal MLV searching algorithm for tree circuits, and a genetic
algorithm to connect the tree circuits. Our experimental results
on all the MCNC91 benchmark circuits reveal that 1) the gate
replacement technique alone can achieve 10% leakage current reduction
over the best known IVC methods with no delay penalty
and little area increase; 2) the divide-and-conquer approach outperforms
the best pure IVC method by 24% and the existing control
point insertion method by 12%; and 3) compared with the
leakage achieved by optimal MLV in small circuits, the gate replacement
heuristic and the divide-and-conquer approach can reduce
on average 13% and 17% leakage, respectively
Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks
This paper presents a unified, comprehensive approach
to the design of continuous-time (CT) and discrete-time
(DT) cellular neural networks (CNN) using CMOS current-mode
analog techniques. The net input signals are currents instead
of voltages as presented in previous approaches, thus avoiding
the need for current-to-voltage dedicated interfaces in image
processing tasks with photosensor devices. Outputs may be either
currents or voltages. Cell design relies on exploitation of current
mirror properties for the efficient implementation of both linear
and nonlinear analog operators. These cells are simpler and
easier to design than those found in previously reported CT
and DT-CNN devices. Basic design issues are covered, together
with discussions on the influence of nonidealities and advanced
circuit design issues as well as design for manufacturability
considerations associated with statistical analysis. Three prototypes
have been designed for l.6-pm n-well CMOS technologies.
One is discrete-time and can be reconfigured via local logic for
noise removal, feature extraction (borders and edges), shadow
detection, hole filling, and connected component detection (CCD)
on a rectangular grid with unity neighborhood radius. The other
two prototypes are continuous-time and fixed template: one for
CCD and other for noise removal. Experimental results are given
illustrating performance of these prototypes
Chapter One – An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques
Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years. Both computer architects and circuit designers intent to reduce power and energy (without a performance degradation) at all design levels, as it is currently the main obstacle to continue with further scaling according to Moore's law. The aim of this survey is to provide a comprehensive overview of power- and energy-efficient “state-of-the-art” techniques. We classify techniques by component where they apply to, which is the most natural way from a designer point of view. We further divide the techniques by the component of power/energy they optimize (static or dynamic), covering in that way complete low-power design flow at the architectural level. At the end, we conclude that only a holistic approach that assumes optimizations at all design levels can lead to significant savings.Peer ReviewedPostprint (published version
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