Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis

This thesis presents thermal and electrical parasitic modeling approaches for layout synthesis of Multi-Chip Power Modules (MCPMs). MCPMs integrate power semiconductor devices and drive electronics into a single package. As the switching frequency of power devices increases, the size of the passive components are greatly reduced leading to gains in efficiency and cost reduction. In order to increase switching frequency, electrical parasitics in MCPMs need to be reduced through tighter electronic integrations and smaller packages. As package size is decreased, temperature increases due to less heat dissipation capability. Thus, it is crucial to consider both thermal and electrical parasitics in order to avoid premature device failure. Traditionally, the evaluation of the temperature and electrical parasitics of an MCPM requires the layout to be changed iteratively by hand and verified via finite element analysis (FEA) tools. The novel thermal and electrical parasitics models developed in this thesis predict temperature and electrical parasitics of an MCPM according to varied layouts. Multi-Objective optimization methods are applied to the models to find optimal layouts and tradeoffs of MCPM layouts

Computation of power plane pair inductance, measurement of multiple switching current components and switching current measurement for multiple ICs with an island structure

The first part of the thesis presents the computation of power / ground plane pair inductance based on Partial Element Equivalent Circuit (PEEC) method in power distribution network (PDN) design. An efficient approach for the inductance computation is investigated. Speed-up techniques are employed include using the faster decay of mutual coupling due to the differential currents (same magnitude but opposite directions) in the two planes. Also, an approximate rectangular mesh reduction method is introduced which allows a local increase in mesh density. The second part presents a measurement-based data-processing approach to obtain parameters of multiple current components through a bulk decoupling capacitor for power integrity studies. A lab-made low-cost current probe is developed to measure the induced voltage due to the time-varying switching current. Then, a post data-processing procedure is introduced to separate and obtain the parameters of multiple current components. The third part proposes a measurement methodology, when IC information is not available, to obtain the equivalent switching current of each IC in the case where multiple ICs are connected to a common power island structure. Time-domain oscilloscope measurements are used to capture the noise-voltage waveforms at a few locations in the power island. Combining with the multi-port frequency-domain S-parameter measurement among the same locations, an equivalent switching current for each IC is calculated. The proposed method is validated at a different location in the power island by comparing the calculated noise voltage using the equivalent switching currents as excitations with the actual measured noise voltage --Abstract, page iv

Modeling and characterization of on-chip interconnects, inductors and transformers

Ph.DNUS-SUPELEC JOINT PH.D. PROGRAMM

Skin-Effect Loss Models for Time- and Frequency-Domain PEEC Solver

published_or_final_versio

Inductors in high-performance silicon radio frequency integrated circuits : analysis, modeling, and design considerations

Spiral inductors are a key component of mixed-signal and analog integrated circuits (IC's). Such circuits are often fabricated using silicon-based technology, owing to the inherent low-cost and high volume production aspects. However, semiconducting substrate materials such as silicon can have adverse effects on spiral inductor performance due to the lossy nature of the material. Since the operating requirements of many high performance IC's demand reactive components that have high Quality Factor's (Q's), and are thus low loss devices, the need for accurate modeling of such structures over lossy substrate media is key to successful circuit design. The Q's of commonly available off-chip inductors are in the range of 50- 100 for frequencies ranging up to a few gigahertz. Since off-chip inductors must be connected through package pins, solder bumps, etc., which all contribute additional loss and thus lower the apparent Q of an external device, the typical on-chip Q requirement for a given RFIC design is generally lower than that for an off-chip spiral solution. However, a spiral inductor that was designed and fabricated originally in a low loss technology such as thin-film alumina may have substantially worse performance in regard to Q if it is used in a silicon-based technology, owing to the conductive substrate. For this reason, it is imperative that semiconducting substrate effects be accurately accounted for by any modeling effort for monolithic spirals in RFICs. This thesis presents a complete modeling solution for both single and multi-level spiral inductors over lossy silicon substrates, along with design considerations and methods for mitigation of the undesirable performance effects of semiconducting substrates. The modeling solution is based on Spectral Domain Approach (SDA) solutions for frequency dependent complex capacitive (i.e. both capacitance and conductance) parasitic elements combined with a quasi-magnetostatic field solution for calculation of the frequency dependent complex inductive (i.e. both inductance and resistance) terms. The effects of geometry and process variations are considered as well as the incorporation of Patterned Ground Shields (PGS) for the purpose of Q enhancement. Proposals for future extensions of this work are discussed in the concluding chapter

Modelling and analysis of crosstalk in scaled CMOS interconnects

The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system

Modeling and Design of Interconnects and Passive Components for Millimeter-Wave Integrated Circuits in Silicon

For mmWave Integrated Circuit (IC) design, co-integration of passives can reduce size and power consumption, increase reliability, and reduce overall cost. However, skin and proximity effects in the metallization are aggravated at mmWave frequencies, resulting in increased attenuation and degradation of overall performance. Furthermore, tight integration of passive components (to reduce the die size) poses additional design challenges due to the complicated electromagnetic couplings between the components in close proximity. Other parasitic effects such as dummy metal fill parasitics and substrate eddy current loss, the impact of process variability and uncertainty are also more prominent at mmWave frequencies. In this thesis, scalable compact modeling techniques based on the Principle of Electromagnetic Similitude and additionally developed methods of complexity reduction are presented. Scalable and compact equivalent circuit models for on-chip microstrip and Coplanar Waveguide (CPW) are developed and validated by both electro-magnetic (EM) simulations and on-wafer measurements. Furthermore, a more general field-based scalable modeling approach for multi-conductor interconnects (e.g., coupled CPWs) and more complicated passives is presented. The field-based approach has been applied and validated for modeling mmWave inductors, including the impact of metal fills and substrate eddy-current effects. Scalable models to capture the magnetic coupling between spiral inductors are presented and a compact layout strategy for reduction of magnetic coupling is proposed. The scalable and compact models include multi-physics effects such as temperature dependency and can also be utilized to study the impact of the process variations efficiently