Design abstraction for autonomous adaptive hardware systems on FPGAs

Adaptive hardware is gaining importance with the emergence of more autonomous systems that must process large volumes of sensor data and react within tight deadlines. To support such computation within the constraints of embedded deployments, a blend of high throughput hardware processing and adaptive control is required. FPGAs offer an ideal platform for implementing such systems by virtue of their hardware flexibility and sensor interfacing capabilities. FPGA SoCs are specifically well suited offering capable embedded processors that are tightly coupled with a flexible high performance FPGA fabric. This paper explores existing work on adaptive hardware systems before proposing a general model and implementation approach tailored towards these modern FPGA architectures, concluding with pointers for research in this emerging field

Evolvable Embryonics: 2-in-1 Approach to Self-healing Systems

This paper covers the authors’ recent research in the area of evolutionary design optimisation in electronic application domain (Evolvable Hardware). This will be also presented in the context of biologically inspired systems where Evolvable Hardware is concerned with evolutionary synthesis of self-healing systems and potentially hardware capable of online adaptation to dynamically changing environment. We will also illustrate how EAs can produce novel and unintuitive design solutions, and possibly new design principles. The novelty of this research project addresses this compelling change in the traditional landscape of the associated research disciplines by seeking to provide a novel biologically inspired mechanism to support the design optimisation of self-healing architectures, that is Evolvable-Embryonics

Autonomous Recovery Of Reconfigurable Logic Devices Using Priority Escalation Of Slack

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria

Special Session on Industry 4.0

No abstract available

Using Partial Reconfiguration for SoC Design and Implementation

Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned. This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the pape

Demonstration of Transformable Manufacturing Systems through the Evolvable Assembly Systems Project

© 2019 SAE International. All Rights Reserved. Evolvable Assembly Systems is a five year UK research council funded project into flexible and reconfigurable manufacturing systems. The principal goal of the research programme has been to define and validate the vision and support architecture, theoretical models, methods and algorithms for Evolvable Assembly Systems as a new platform for open, adaptable, context-aware and cost effective production. The project is now coming to a close; the concepts developed during the project have been implemented on a variety of demonstrators across a number of manufacturing domains including automotive and aerospace assembly. This paper will show the progression of demonstrators and applications as they increase in complexity, specifically focussing on the Future Automated Aerospace Assembly Phase 1 technology demonstrator (FA3D). The FA3D Phase 1 demonstrated automated assembly of aerospace products using precision robotic processes in conjunction with low-cost reconfigurable fixturing supported by large volume metrology. This was underpinned by novel agent-based control for transformable batch-size-of-one production. The paper will conclude by introducing Phase 2 of the Future Automated Aerospace Assembly Demonstrator - currently in development - that will translate the Evolvable Assembly Systems research to a higher technology readiness level and address the challenges of scalable and transformable manufacturing systems

Hexarray: A Novel Self-Reconfigurable Hardware System

Evolvable hardware (EHW) is a powerful autonomous system for adapting and finding solutions within a changing environment. EHW consists of two main components: a reconfigurable hardware core and an evolutionary algorithm. The majority of prior research focuses on improving either the reconfigurable hardware or the evolutionary algorithm in place, but not both. Thus, current implementations suffer from being application oriented and having slow reconfiguration times, low efficiencies, and less routing flexibility. In this work, a novel evolvable hardware platform is proposed that combines a novel reconfigurable hardware core and a novel evolutionary algorithm. The proposed reconfigurable hardware core is a systolic array, which is called HexArray. HexArray was constructed using processing elements with a redesigned architecture, called HexCells, which provide routing flexibility and support for hybrid reconfiguration schemes. The improved evolutionary algorithm is a genome-aware genetic algorithm (GAGA) that accelerates evolution. Guided by a fitness function the GAGA utilizes context-aware genetic operators to evolve solutions. The operators are genome-aware constrained (GAC) selection, genome-aware mutation (GAM), and genome-aware crossover (GAX). The GAC selection operator improves parallelism and reduces the redundant evaluations. The GAM operator restricts the mutation to the part of the genome that affects the selected output. The GAX operator cascades, interleaves, or parallel-recombines genomes at the cell level to generate better genomes. These operators improve evolution while not limiting the algorithm from exploring all areas of a solution space. The system was implemented on a SoC that includes a programmable logic (i.e., field-programmable gate array) to realize the HexArray and a processing system to execute the GAGA. A computationally intensive application that evolves adaptive filters for image processing was chosen as a case study and used to conduct a set of experiments to prove the developed system robustness. Through an iterative process using the genetic operators and a fitness function, the EHW system configures and adapts itself to evolve fitter solutions. In a relatively short time (e.g., seconds), HexArray is able to evolve autonomously to the desired filter. By exploiting the routing flexibility in the HexArray architecture, the EHW has a simple yet effective mechanism to detect and tolerate faulty cells, which improves system reliability. Finally, a mechanism that accelerates the evolution process by hiding the reconfiguration time in an “evolve-while-reconfigure” process is presented. In this process, the GAGA utilizes the array routing flexibility to bypass cells that are being configured and evaluates several genomes in parallel

On microelectronic self-learning cognitive chip systems

After a brief review of machine learning techniques and applications, this Ph.D. thesis examines several approaches for implementing machine learning architectures and algorithms into hardware within our laboratory. From this interdisciplinary background support, we have motivations for novel approaches that we intend to follow as an objective of innovative hardware implementations of dynamically self-reconfigurable logic for enhanced self-adaptive, self-(re)organizing and eventually self-assembling machine learning systems, while developing this new particular area of research. And after reviewing some relevant background of robotic control methods followed by most recent advanced cognitive controllers, this Ph.D. thesis suggests that amongst many well-known ways of designing operational technologies, the design methodologies of those leading-edge high-tech devices such as cognitive chips that may well lead to intelligent machines exhibiting conscious phenomena should crucially be restricted to extremely well defined constraints. Roboticists also need those as specifications to help decide upfront on otherwise infinitely free hardware/software design details. In addition and most importantly, we propose these specifications as methodological guidelines tightly related to ethics and the nowadays well-identified workings of the human body and of its psyche

Diagnosis of an EPS module

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e ComputadoresThis thesis addresses and contextualizes the problem of diagnostic of an Evolvable Production System (EPS). An EPS is a complex and lively entity composed of intelligent modules that interact through bio-inspired mechanisms, to ensure high system availability and seamless reconfiguration. The actual economic situation together with the increasing demand of high quality and low priced customized products imposed a shift in the production policies of enterprises. Shop floors have to become more agile and flexible to accommodate the new production paradigms. Rather than selling products enterprises are establishing a trend of offering services to explore business opportunities. The new production paradigms, potentiated by the advances in Information Technologies (IT), especially in web related standards and technologies as well as the progressive acceptance of the multi-agent systems (MAS) concept and related technologies, envision collections of modules whose individual and collective function adapts and evolves ensuring the fitness and adequacy of the shop floor in tackling profitable but volatile business opportunities. Despite the richness of the interactions and the effort set in modelling them, their potential to favour fault propagation and interference, in these complex environments, has been ignored from a diagnostic point of view. With the increase of distributed and autonomous components that interact in the execution of processes current diagnostic approaches will soon be insufficient. While current system dynamics are complex and to a certain extent unpredictable the adoption of the next generation of approaches and technologies comes at the cost of a yet increased complexity.Whereas most of the research in such distributed industrial systems is focused in the study and establishment of control structures, the problem of diagnosis has been left relatively unattended. There are however significant open challenges in the diagnosis of such modular systems including: understanding fault propagation and ensuring scalability and co-evolution. This work provides an implementation of a state-of-the-art agent-based interaction-oriented architecture compliant with the EPS paradigm that supports the introduction of a new developed diagnostic algorithm that has the ability to cope with the modern manufacturing paradigm challenges and to provide diagnostic analysis that explores the network dimension of multi-agent systems