4,376 research outputs found

    Improving EHW performance introducing a new decomposition strategy

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    This paper describes a new type of decomposition strategy for Evolvable Hardware, which tackles the problem of scalability. Several logic circuits from the MCNC benchmark have been evolved and compared with other Evolvable Hardware techniques. The results demonstrate that the proposed method improves the evolution of logic circuits in terms of time and fitness function in comparison with BIE and standard EHW

    Artificial in its own right

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    Artificial Cells, , Artificial Ecologies, Artificial Intelligence, Bio-Inspired Hardware Systems, Computational Autopoiesis, Computational Biology, Computational Embryology, Computational Evolution, Morphogenesis, Cyborgization, Digital Evolution, Evolvable Hardware, Cyborgs, Mathematical Biology, Nanotechnology, Posthuman, Transhuman

    Generalized disjunction decomposition for evolvable hardware

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    Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the(1+lambda)(1 + lambda)evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

    Generalized disjunction decomposition for the evolution of programmable logic array structures

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    Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has shown one of its main deficiencies, when applied to solving real world applications, to be scalability. In the past few years several techniques have been proposed to avoid and/or solve this problem. Generalized disjunction decomposition (GDD) is one of these proposed methods. GDD was successful for the evolution of large combinational logic circuits based on a FPGA structure when used together with bi-directional incremental evolution and with (1+ë) evolution strategy. In this paper a modified generalized disjunction decomposition, together with a recently introduced multi-population genetic algorithm, are implemented and tested for its scalability for solving large combinational logic circuits based on Programmable Logic Array (PLA) structures

    An extrinsic function-level evolvable hardware approach

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    The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in first time. The new representation of logic gate in extrinsic EHW allows us to describe behaviour of any multi-input multi-output logic function. The circuit is represented in the form of connections and functionalities of a rectangular array of building blocks. Each building block can implement primitive logic function or any multi-input multi-output logic function defined in advance. The method has been tested on evolving logic circuits using half adder, full adder and multiplier. The effectiveness of this approach is investigated for multiple-valued and binary arithmetical functions. For these functions either method appears to be much more efficient than similar approach with two-input one-output cell representation

    Bidirectional incremental evolution in extrinsic evolvable hardware

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    Evolvable Hardware (EHW) has been proposed as a new technique to design complex systems. Often, complex systems turn out to be very difficult to evolve. The problem is that a general strategy is too difficult for the evolution process to discover directly. This paper proposes a new approach that performs incremental evolution in two directions: from complex system to sub-systems and from sub-systems back to complex system. In this approach, incremental evolution gradually decomposes a complex problem into some sub-tasks. In a second step, we gradually make the tasks more challenging and general. Our approach automatically discovers the sub-tasks, their sequence as well as circuit layout dimensions. Our method is tested in a digital circuit domain and compared to direct evolution. We show that our bidirectional incremental approach can handle more complex, harder tasks and evolve them more effectively, then direct evolution
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