Generalized disjunction decomposition for evolvable hardware

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the “generalized disjunction decomposition” (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the$(1 + lambda)$evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided

ENHANCING PERFORMANCE OF ITERATIVE HEURISTICS FOR VLSI NETLIST PARTITIONING

ABSTRACT In this paper we, present a new heuristic called PowerFM which is a modification of the well-known Fidducia Mattheyeses algorithm for VLSI netlist partitioning. PowerFM considers the minimization of power consumption due to the nets cut. The advantages of using PowerFM as an initial solution generator for other iterative algorithms, in panicular Genetic Algorithm (GA) and Tabu Search (TS), for multiobjective optimization is investigated. A series of experiments are conducted on ISCAS-85/89 benchmark circuits to evaluate the efficiency of the PawerFM algorithm. Results suggest that this heuristic would provide a good starting solution for multiobjective optimization using iterative algorithms

EFFICIENT COMBINATIONAL CIRCUITS DESIGN THROUGH FUZZIFIED ANT COLONY OPTIMIZATION ALGORITHM

With the increasing demand for high quality, more efficient and less area circuits, the problem of logic circuit design has become a multiobjective optimization problem. In this paper, a multiobjective optimization of logic circuits based on a fuzzified Ant Colony (ACO) algorithm is presented. The results obtained using the proposed algorithm are compared to those obtained using SIS in terms of area, delay and power. It is shown that the circuits produced by the proposed algorithm are better as compared to those obtained by SIS

Evolvable Embryonics: 2-in-1 Approach to Self-healing Systems

This paper covers the authors’ recent research in the area of evolutionary design optimisation in electronic application domain (Evolvable Hardware). This will be also presented in the context of biologically inspired systems where Evolvable Hardware is concerned with evolutionary synthesis of self-healing systems and potentially hardware capable of online adaptation to dynamically changing environment. We will also illustrate how EAs can produce novel and unintuitive design solutions, and possibly new design principles. The novelty of this research project addresses this compelling change in the traditional landscape of the associated research disciplines by seeking to provide a novel biologically inspired mechanism to support the design optimisation of self-healing architectures, that is Evolvable-Embryonics

Fuzzified Ant Colony Optimization Algorithm for Efficient Combinational Circuits Synthesis

Abstract- With the increasing demand for high quality, more efficient, less areaand less power circuits, the problem of logic circuit design has become a multiobjective optimization problem. In this paper, multiobjective optimization of logic circuits based on a fnzzified Ant Colony (ACO) algorithm is presented. The results obtained using the proposed algorithm are compared to those obtained using SIS in terms of area, delay and power for some known circuits. It is shown that the circuits produced by the proposed algorithm are better as compared to those obtained by SIS

EFFICIENT COMBINATIONAL CIRCUITS DESIGN THROUGH FUZZIFIED ANT COLONY OPTIMIZATION ALGORITHM

With the increasing demand for high quality, more efficient and less area circuits, the problem of logic circuit design has become a multiobjective optimization problem. In this paper, a multiobjective optimization of logic circuits based on a fuzzified Ant Colony (ACO) algorithm is presented. The results obtained using the proposed algorithm are compared to those obtained using SIS in terms of area, delay and power. It is shown that the circuits produced by the proposed algorithm are better as compared to those obtained by SIS

Analysis of genotype size for an evolvable hardware system

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+lambda) evolution strategy as the core of the evolution