Applications of Emerging Memory in Modern Computer Systems: Storage and Acceleration

In recent year, heterogeneous architecture emerges as a promising technology to conquer the constraints in homogeneous multi-core architecture, such as supply voltage scaling, off-chip communication bandwidth, and application parallelism. Various forms of accelerators, e.g., GPU and ASIC, have been extensively studied for their tradeoffs between computation efficiency and adaptivity. But with the increasing demand of the capacity and the technology scaling, accelerators also face limitations on cost-efficiency due to the use of traditional memory technologies and architecture design. Emerging memory has become a promising memory technology to inspire some new designs by replacing traditional memory technologies in modern computer system. In this dissertation, I will first summarize my research on the application of Spin-transfer torque random access memory (STT-RAM) in GPU memory hierarchy, which offers simple cell structure and non-volatility to enable much smaller cell area than SRAM and almost zero standby power. Then I will introduce my research about memristor implementation as the computation component in the neuromorphic computing accelerator, which has the similarity between the programmable resistance state of memristors and the variable synaptic strengths of biological synapses to simplify the realization of neural network model. At last, a dedicated interconnection network design for multicore neuromorphic computing system will be presented to reduce the prominent average latency and power consumption brought by NoC in a large size neuromorphic computing system

Analysis on Supercapacitor Assisted Low Dropout (SCALDO) Regulators

State-of-the-art electronic systems employ three fundamental techniques for DC-DC converters: (a) switch-mode power supplies (SMPS); (b) linear power supplies; (c) switched capacitor (charge pump) converters. In practical systems, these three techniques are mixed to provide a complex, but elegant, overall solution, with energy efficiency, effective PCB footprint, noise and transient performance to suit different electronic circuit blocks. Switching regulators have relatively high end-to-end efficiency, in the range of 70 to 93%, but can have issues with output noise and EMI/RFI emissions. Switched capacitor converters use a set of capacitors for energy storage and conversion. In general, linear regulators have low efficiencies in the range 30 to 60%. However, they have outstanding output characteristics such as low noise, excellent transient response to load current fluctuations, design simplicity and low cost design which are far superior to SMPS. Given the complex situation in switch-mode converters, low dropout (LDO) regulators were introduced to address the equirements of noise-sensitive and fast transient loads in portable devices. A typical commercial off-the-shelf LDO has its input voltage slightly higher than the desired regulated output for optimal efficiency. The approximate efficiency of a linear regulator, if the power consumed by the control circuits is negligible, can be expressed by the ratio of Vo/Vin. A very low frequency supercapacitor circulation technique can be combined with commercial low dropout regulator ICs to significantly increase the end-to-end efficiency by a multiplication factor in the range of 1.33 to 3, compared to the efficiency of a linear regulator circuit with the same input-output voltages. In this patented supercapacitor-assisted low dropout (SCALDO) regulator technique developed by a research team at the University of Waikato, supercapacitors are used as lossless voltage droppers, and the energy reuse occurs at very low frequencies in the range of less than ten hertz, eliminating RFI/EMI concerns. This SCALDO technique opens up a new approach to design step-down, DC-DC converters suitable for processor power supplies with very high end-to-end efficiency which is closer to the efficiencies of practical switching regulators, while maintaining the superior output specifications of a linear design. Furthermore, it is important to emphasize that the SCALDO technique is not a variation of well-known switched capacitor DC-DC converters. In this thesis, the basic SCALDO concept is further developed to achieve generalised topologies, with the relevant theory that can be applied to a converter with any input-output step-down voltage combination. For these generalised topologies, some important design parameters, such as the number of supercapacitors, switching matrix details and efficiency improvement factors, are derived to form the basis of designing SCALDO regulators. With the availability of commercial LDO ICs with output current ratings up to 10 A, and thin-prole supercapacitors with DC voltage ratings from 2.3 to 5.5 V, several practically useful, medium-current SCALDO prototypes: 12V-to-5V, 5V-to-2V, 5.5V-to-3.3V have been developed. Experimental studies were carried out on these SCALDO prototypes to quantify performance in terms of line regulation, load regulation, efficiency and transient response. In order to accurately predict the performance and associated waveforms of the individual phases (charge, discharge and transition) of the SCALDO regulator, Laplace transform-based theory for supercapacitor circulation is developed, and analytical predictions are compared with experimental measurements for a 12V-to-5V prototype. The analytical results tallied well with the practical waveforms observed in a 12V-to-5V converter, indicating that the SCALDO technique can be generalized to other versatile configurations, and confirming that the simplified assumptions used to describe the circuit elements are reasonable and justifiable. After analysing the performance of several SCALDO prototypes, some practical issues in designing SCALDO regulators have been identified. These relate to power losses and implications for future development of the SCALDO design

A study on hardware design for high performance artificial neural network by using FPGA and NoC

制度:新 ; 報告番号:甲3421号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574

C-Band Airport Surface Communications System Standards Development, Phase I

This document is being provided as part of ITT's NASA Glenn Research Center Aerospace Communication Systems Technical Support (ACSTS) contract NNC05CA85C, Task 7: "New ATM Requirements--Future Communications, C-Band and L-Band Communications Standard Development." The proposed future C-band (5091- to 5150-MHz) airport surface communication system, referred to as the Aeronautical Mobile Airport Communications System (AeroMACS), is anticipated to increase overall air-to-ground data communications systems capacity by using a new spectrum (i.e., not very high frequency (VHF)). Although some critical services could be supported, AeroMACS will also target noncritical services, such as weather advisory and aeronautical information services as part of an airborne System Wide Information Management (SWIM) program. AeroMACS is to be designed and implemented in a manner that will not disrupt other services operating in the C-band. This report defines the AeroMACS concepts of use, high-level system requirements, and architecture; the performance of supporting system analyses; the development of AeroMACS test and demonstration plans; and the establishment of an operational AeroMACS capability in support of C-band aeronautical data communications standards to be advanced in both international (International Civil Aviation Organization, ICAO) and national (RTCA) forums. This includes the development of system parameter profile recommendations for AeroMACS based on existing Institute of Electrical and Electronics Engineering (IEEE) 802.16e- 2009 standard

Performance of MIMO Schemes in Radio-over-fibre-based Distributed Antenna System

The research presented in this thesis has focused on the use of MIMO wireless communications in a RoF-based DAS to improve wireless coverage and capacity performance in an indoor environment. The aim is to analyse the practical issues that cause throughput to deteriorate when commercial MIMO APs are used in a RoF-DAS, and also to verify that improved performance - lower error rates and higher capacities - can be achieved by a large physical separation between the RAUs when specific multi-antenna scheme algorithms are used. The performance of an IEEE 802.11n MIMO-supported AP and IEEE 802.11g spatial-diversity-supported AP are investigated in a RoF-DAS when different fibre lengths are connecting the AP in the central unit to the RAUs, and when the RAUs are widely separated. The analysis indicates that for MIMO, the throughput drops rapidly due to severe ISI caused by differential delay when the fibre-length difference exceeds a certain distance, while for spatial diversity high throughputs can be maintained even at large fibre-length difference. Further, it was observed that largely separated RAU may lead to power imbalances and the throughput drops in specific wireless user's positions when the received power imbalance was above 12-15dB for MIMO-supported AP, while for spatial-diversity-supported AP the power imbalance does not affect the throughput. The majority of previous works on RoF-DAS for improving MIMO systems were based on commercial products and the specific algorithms used within these products are unknown. An investigation was carried out at microwave frequency with SIMO algorithms in RoF-DAS uplink, MISO and MIMO algorithms in RoF-DAS downlink, and compared with the performance of a SISO system. This investigation was later extended to millimetre-wave frequency where larger bands of frequency are available enabling the possibility of wider bandwidth and higher data rates. The result shows significantly reduced error rate and modestly increased capacity for a wireless 1x2 SIMO uplink using MRC algorithm and 2x1 MISO downlink using Alamouti STBC algorithm. Also, error rate was reduced for a wireless 2x2 MIMO downlink using the zero-forcing algorithm while, most importantly, greatly increased capacity was achieved through the spatial multiplexing gain

Device and Circuit Level EMI Induced Vulnerability: Modeling and Experiments

Electro-magnetic interference (EMI) commonly exists in electronic equipment containing semiconductor-based integrated circuits (ICs). Metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the ICs may be disrupted under EMI conditions due to transient voltage-current surges, and their internal states may change undesirably. In this work, the vulnerabilities of silicon MOSFETs under EMI are studied at the device and the circuit levels, categorized as non-permanent upsets (``Soft Errors'') and permanent damages (``Hard Failures''). The Soft Errors, such as temporary bit errors and waveform distortions, may happen or be intensified under EMI, as the transient disruptions activate unwanted and highly non-linear changes inside MOSFETs, such as Impact Ionization and Snapback. The system may be corrected from the erroneous state when the EMI condition is removed. We simulate planar silicon n-type MOSFETs at the device level to study the physical mechanisms leading to or complicate the short-term, signal-level Soft Errors. We experimentally tested commercially available MOSFET devices. Not included in regular MOSFET models, exponential-like current increases as the terminal voltage increases are observed and explained using the device-level knowledge. We develop a compact Soft Error model, compatible with circuit simulators using lumped (or compact-model) components and closed-form expressions, such as SPICE, and calibrate it with our in-house experimental data using an in-house extraction technique based on the Genetic Algorithm. Example circuits are simulated using the extracted device model and under EMI-induced transient disruptions. The EMI voltage-current disruptions may also lead to permanent Hard Failures that cannot be repaired without replacement. One type of Hard Failures, the MOSFET gate dielectric (or ``oxide'') breakdown, can result in input-output relation changes and additional thermal runaway. We have fabricated individual MOSFET devices at the FabLab at the University of Maryland NanoCenter. We experimentally stress-test the fabricated devices and observe the rapid, permanent oxide breakdown. Then, we simulate a nano-scale FinFET device with ultra-thin gate oxide at the device level. Then, we apply the knowledge from our experiments to the simulated FinFET, producing a gate oxide breakdown Hard Failure circuit model. The proposed workflow enables the evaluation of EMI-induced vulnerabilities in circuit simulations before actual fabrication and experiments, which can help the early-stage prototyping process and reduce the development time

C-Band Airport Surface Communications System Standards Development. Phase II Final Report. Volume 1: Concepts of Use, Initial System Requirements, Architecture, and AeroMACS Design Considerations

This report is provided as part of ITT s NASA Glenn Research Center Aerospace Communication Systems Technical Support (ACSTS) contract NNC05CA85C, Task 7: New ATM Requirements-Future Communications, C-Band and L-Band Communications Standard Development and was based on direction provided by FAA project-level agreements for New ATM Requirements-Future Communications. Task 7 included two subtasks. Subtask 7-1 addressed C-band (5091- to 5150-MHz) airport surface data communications standards development, systems engineering, test bed and prototype development, and tests and demonstrations to establish operational capability for the Aeronautical Mobile Airport Communications System (AeroMACS). Subtask 7-2 focused on systems engineering and development support of the L-band digital aeronautical communications system (L-DACS). Subtask 7-1 consisted of two phases. Phase I included development of AeroMACS concepts of use, requirements, architecture, and initial high-level safety risk assessment. Phase II builds on Phase I results and is presented in two volumes. Volume I (this document) is devoted to concepts of use, system requirements, and architecture, including AeroMACS design considerations. Volume II describes an AeroMACS prototype evaluation and presents final AeroMACS recommendations. This report also describes airport categorization and channelization methodologies. The purposes of the airport categorization task were (1) to facilitate initial AeroMACS architecture designs and enable budgetary projections by creating a set of airport categories based on common airport characteristics and design objectives, and (2) to offer high-level guidance to potential AeroMACS technology and policy development sponsors and service providers. A channelization plan methodology was developed because a common global methodology is needed to assure seamless interoperability among diverse AeroMACS services potentially supplied by multiple service providers

Smart Metering Technology and Services

Global energy context has become more and more complex in the last decades; the raising prices of fuels together with economic crisis, new international environmental and energy policies that are forcing companies. Nowadays, as we approach the problem of global warming and climate changes, smart metering technology has an effective use and is crucial for reaching the 2020 energy efficiency and renewable energy targets as a future for smart grids. The environmental targets are modifying the shape of the electricity sectors in the next century. The smart technologies and demand side management are the key features of the future of the electricity sectors. The target challenges are coupling the innovative smart metering services with the smart meters technologies, and the consumers' behaviour should interact with new technologies and polices. The book looks for the future of the electricity demand and the challenges posed by climate changes by using the smart meters technologies and smart meters services. The book is written by leaders from academia and industry experts who are handling the smart meters technologies, infrastructure, protocols, economics, policies and regulations. It provides a promising aspect of the future of the electricity demand. This book is intended for academics and engineers who are working in universities, research institutes, utilities and industry sectors wishing to enhance their idea and get new information about the smart meters