2,104 research outputs found
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
A programmable microsystem using system-on-chip for real-time biotelemetry
A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm × 5 mm silicon chip using a 0.6 μm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm × 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10<sup>-</sup><sup>3</sup> using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
Image convolution operations in digital computer systems are usually
very expensive operations in terms of resource consumption (processor
resources and processing time) for an efficient Real-Time application. In these
scenarios the visual information is divided in frames and each one has to be
completely processed before the next frame arrives. Recently a new method for
computing convolutions based on the neuro-inspired philosophy of spiking
systems (Address-Event-Representation systems, AER) is achieving high
performances. In this paper we present two FPGA implementations of AERbased
convolution processors that are able to work with 64x64 images and
programmable kernels of up to 11x11 elements. The main difference is the use
of RAM for integrators in one solution and the absence of integrators in the
second solution that is based on mapping operations. The maximum equivalent
operation rate is 163.51 MOPS for 11x11 kernels, in a Xilinx Spartan 3 400
FPGA with a 50MHz clock. Formulations, hardware architecture, operation
examples and performance comparison with frame-based convolution
processors are presented and discussed.Ministerio de Ciencia e InnovaciĂłn TEC2006-11730-C03-02Junta de AndalucĂa P06-TIC-0141
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