595 research outputs found
A survey on scheduling and mapping techniques in 3D Network-on-chip
Network-on-Chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution.
NoCs enable communications between on-chip Intellectual Property (IP) cores and
allow those cores to achieve higher performance by outsourcing their
communication tasks. Mapping and Scheduling methodologies are key elements in
assigning application tasks, allocating the tasks to the IPs, and organising
communication among them to achieve some specified objectives. The goal of this
paper is to present a detailed state-of-the-art of research in the field of
mapping and scheduling of applications on 3D NoC, classifying the works based
on several dimensions and giving some potential research directions
Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip
Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures.
Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate
permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the
permanent faults in application cores while placing the spare cores onto NoC topologies. However, these
techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the
fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper
presents the flexible placement of spare core onto Torus topology-based NoC design by considering core
faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear
Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the
placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing
algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology
using an FPGA. Experiments have been done by taking different multimedia and synthetic application
benchmarks. This has been done in both static and dynamic simulation environments followed by hardware
implementation. In the static simulation environment, the experimentations are carried out by scaling the
network size and router faults in the network. The results obtained from our approach outperform the
methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic
Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size,
our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication
cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the
router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the
approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average
improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the
hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms
of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of
the proposed approach over the approaches presented in the literature.publishedVersio
Design and Implementation of High QoS 3D-NoC using Modified Double Particle Swarm Optimization on FPGA
One technique to overcome the exponential growth bottleneck is to increase the number of cores on a processor, although having too many cores might cause issues including chip overheating and communication blockage. The problem of the communication bottleneck on the chip is presently effectively resolved by networks-on-chip (NoC). A 3D stack of chips is now possible, thanks to recent developments in IC manufacturing techniques, enabling to reduce of chip area while increasing chip throughput and reducing power consumption. The automated process associated with mapping applications to form three-dimensional NoC architectures is a significant new path in 3D NoC research. This work proposes a 3D NoC partitioning approach that can identify the 3D NoC region that has to be mapped. A double particle swarm optimization (DPSO) inspired algorithmic technique, which may combine the characteristics having neighbourhood search and genetic architectures, also addresses the challenge of a particle swarm algorithm descending into local optimal solutions. Experimental evidence supports the claim that this hybrid optimization algorithm based on Double Particle Swarm Optimisation outperforms the conventional heuristic technique in terms of output rate and loss in energy. The findings demonstrate that in a network of the same size, the newly introduced router delivers the lowest loss on the longest path. Three factors, namely energy, latency or delay, and throughput, are compared between the suggested 3D mesh ONoC and its 2D version. When comparing power consumption between 3D ONoC and its electronic and 2D equivalents, which both have 512 IP cores, it may save roughly 79.9% of the energy used by the electronic counterpart and 24.3% of the energy used by the latter. The network efficiency of the 3D mesh ONoC is simulated by DPSO in a variety of configurations. The outcomes also demonstrate an increase in performance over the 2D ONoC. As a flexible communication solution, Network-On-Chips (NoCs) have been frequently employed in the development of multiprocessor system-on-chips (MPSoCs). By outsourcing their communication activities, NoCs permit on-chip Intellectual Property (IP) cores to communicate with one another and function at a better level. The important components in assigning application duties, distributing the work to the IPs, and coordinating communication among them are mapping and scheduling methods. This study aims to present an entirely advanced form of research in the area of 3D NoC mapping and scheduling applications, grouping the results according to various parameters and offering several suggestions for further research
A Topology-Independent Mapping Technique for Application-Specific Networks-on-Chip
The design of Networks-on-Chip (NoCs) involves several key issues, including the topological mapping, that is, the mapping of the processing elements or Intellectual Properties (IPs) to the network nodes. Although several proposals have been focused on topological mapping last years, this topic is still an open issue. In this paper, we propose, in an extended manner, a topology-independent mapping technique for application-specific NoCs that can be used with regular or irregular topologies, and with any routing algorithm. This technique globally matches the communication pattern generated by the IPs with the available network bandwidth in the different parts of the network. The evaluation results show that the proposed technique can provide better performance than other mapping techniques not only in terms of average latency and network throughput, but also in terms of power consumption
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