Development of a Low-Noise High Common-Mode-Rejection Instrumentation Amplifier

Several previously used instrumentation amplifier circuits were examined to find limitations and possibilities for improvement. One general configuration is analyzed in detail, and methods for improvement are enumerated. An improved amplifier circuit is described and analyzed with respect to common mode rejection and noise. Experimental data are presented showing good agreement between calculated and measured common mode rejection ratio and equivalent noise resistance. The amplifier is shown to be capable of common mode rejection in excess of 140 db for a trimmed circuit at frequencies below 100 Hz and equivalent white noise below 3.0 nv/square root of Hz above 1000 Hz

Asynchronous Phase Comparator for Characterization of Devices for PMUs Calibrator

This paper reports recent progress in developing a new asynchronous digital phase comparator for the precision measurement of phase difference of voltage ratio devices and calibration of functional elements of phasor measurement units (PMUs) calibrator. The phase error of the proposed digital comparator is below 300 nrad at 50 Hz and 100 μrad at 100 kHz with applied voltages ranging between 500 mV and 3 V, whereas the phase error of cables and connectors was estimated to be 4 μrad at 1 MHz. Besides resistive dividers, the phase comparator has been employed for the characterization of frequency behavior of phase difference between the output and input of voltage and transconductance amplifiers for a PMUs calibrator. The system can also be an important tool for phase-frequency characterization of devices employed for specific wideband power measurements

Design considerations for a monolithic, GaAs, dual-mode, QPSK/QASK, high-throughput rate transceiver

A monolithic, GaAs, dual mode, quadrature amplitude shift keying and quadrature phase shift keying transceiver with one and two billion bits per second data rate is being considered to achieve a low power, small and ultra high speed communication system for satellite as well as terrestrial purposes. Recent GaAs integrated circuit achievements are surveyed and their constituent device types are evaluated. Design considerations, on an elemental level, of the entire modem are further included for monolithic realization with practical fabrication techniques. Numerous device types, with practical monolithic compatability, are used in the design of functional blocks with sufficient performances for realization of the transceiver

Ka-band Ga-As FET noise receiver/device development

The development of technology for a 30 GHz low noise receiver utilizing GaAs FET devices exclusively is discussed. This program required single and dual-gate FET devices, low noise FET amplifiers, dual-gate FET mixers, and FET oscillators operating at Ka-band frequencies. A 0.25 micrometer gate FET device, developed with a minimum noise figure of 3.3 dB at 29 GHz and an associated gain of 7.4 dB, was used to fabricate a 3-stage amplifier with a minimum noise figure and associated gain of 4.4 dB and 17 dB, respectively. The 1-dB gain bandwidth of this amplifier extended from below 26.5 GHz to 30.5 GHz. A dual-gate mixer with a 2 dB conversion loss and a minimum noise figure of 10 dB at 29 GHz as well as a dielectric resonator stabilized FET oscillator at 25 GHz for the receiver L0. From these components, a hybrid microwave integrated circuit receiver was constructed which demonstrates a minimum single-side band noise figure of 4.6 dB at 29 GHz with a conversion gain of 17 dB. The output power at the 1-dB gain compression point was -5 dBm

Design, Simulation, and Implementation of GmC-based Phase Locked Loop

This study explores the design, simulation, and implementation of a transconductance-based Phase Locked Loop system using GmC filters as main building blocks. The system is broken down to four stages; the band pass filter acting as a reference signal, the voltage controlled oscillator designed at the desired frequency, the phase detector in charge of comparing the difference in phase between the two input signals from the VCO and BPF quadrature outputs, and the loop filter whose signal is then sent to the VCO to track the reference signal of the phase locked loop. All these stages are first simulated and tested using PSPICE models, and later physically implemented and their behavior is examined to evaluate the feasibility of creating a system capable of dealing with RF signals. The results of the simulations are then compared against the real experimental results of the prototypes implemented for the phase locked loop

Design Optimization of Transistors Used for Neural Recording

Neurons cultured directly over open-gate field-effect transistors result in a hybrid device, the neuron-FET. Neuron-FET amplifier circuits reported in the literature employ the neuron-FET transducer as a current-mode device in conjunction with a transimpedance amplifier. In this configuration, the transducer does not provide any signal gain, and characterization of the transducer out of the amplification circuit is required. Furthermore, the circuit requires a complex biasing scheme that must be retuned to compensate for drift. Here we present an alternative strategy based on the design approach to optimize a single-stage common-source amplifier design. The design approach facilitates in circuit characterization of the neuron-FET and provides insight into approaches to improving the transistor process design for application as a neuron-FET transducer. Simulation data for a test case demonstrates optimization of the transistor design and significant increase in gain over a current mode implementation

A high frame rate wearable EIT system using active electrode ASICs for lung respiration and heart rate monitoring

A high specification, wearable, electrical impedance tomography (EIT) system with 32 active electrodes is presented. Each electrode has an application specific integrated circuit (ASIC) mounted on a flexible printed circuit board, which is then wrapped inside a disposable fabric cover containing silver-coated electrodes to form the wearable belt. It is connected to a central hub that operates all the 32 ASICs. Each ASIC comprises a high- performance current driver capable of up to 6 mAp−p output, a voltage buffer for EIT and heart rate signal recording as well as contact impedance monitoring, and a sensor buffer that provides multi-parameter sensing. The ASIC was designed in a CMOS 0.35-μm high-voltage process technology. It operates from ±9-V power supplies and occupies a total die area of 3.9 mm2. The EIT system has a bandwidth of 500 kHz and employs two parallel data acquisition channels to achieve a frame rate of 107 frames/s, the fastest wearable EIT system reported to date. Measured results show that the system has a measurement accuracy of 98.88% and a minimum EIT detectability of 0.86 Q/frame. Its successful operation in capturing EIT lung respiration and heart rate biosignals from a volunteer is demonstrated

A miniature tunable quadrature shadow oscillator with orthogonal control

This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit