Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

VCO start-up and stability analysis using time varying root locus

The oscillator circuit is one of the key components of the communication systems. It is necessary for an oscillator to provide the proper oscillations in order to confirm the stable operation of a communication circuit. There are many different analysis methods of analyzing the start-up and frequency stability of a system, but mostly it fails to analyze properly due to the parasitics involved. Somehow if any of them manages to compute the analysis it would be very complex, difficult and time consuming. The time varying root locus (TVRL) approach can be utilized to analyze the start-up and frequency behavior of different oscillator designs. It is a theoretical based technique that can provide further insights into a circuit designer for oscillator operation. To analyze the start-up behavior, a semi-symbolic TVRL approach can be used with the help of the numerical QZ (Generalized Schur Decomposition) algorithm. By finding the time varying roots of polynomials, TVRL can help to estimate the undesired operating points. A symbolic TVRL analysis is capable of computing the system roots during an oscillation with the help of Muller algorithm. Different numerical and the CAD (Computer Aided Design) tool are involved to implement this theoretical approach. Cadence 45nm CMOS General Process Design Kit (GPDK) helps to design the required schematic and SpectreRF simulator computes the time varying periodic solutions. Maple script can form an admittance matrix which is later used in MATALB to compute the final TVRL trajectories of dominant poles. The corresponding results are then analyzed to detect the failure mechanism which is responsible for relaxation oscillations. In this thesis, an active inductor quadrature voltage controlled oscillator and five stage ring oscillator circuits are proposed to analyze thoroughly with the help of TVRL approach. The above mentioned techniques along with some extra computations have been implemented to verify whether the proposed circuits can overcome the relaxation oscillations and can produce the proper sinusoidal waveforms or there is a need to devise some modifications

Analysis and design of sinusoidal quadrature RC-oscillators

Modern telecommunication equipment requires components that operate in many different frequency bands and support multiple communication standards, to cope with the growing demand for higher data rate. Also, a growing number of standards are adopting the use of spectrum efficient digital modulations, such as quadrature amplitude modulation (QAM) and orthogonal frequency division multiplexing (OFDM). These modulation schemes require accurate quadrature oscillators, which makes the quadrature oscillator a key block in modern radio frequency (RF) transceivers. The wide tuning range characteristics of inductorless quadrature oscillators make them natural candidates, despite their higher phase noise, in comparison with LC-oscillators. This thesis presents a detailed study of inductorless sinusoidal quadrature oscillators. Three quadrature oscillators are investigated: the active coupling RC-oscillator, the novel capacitive coupling RCoscillator, and the two-integrator oscillator. The thesis includes a detailed analysis of the Van der Pol oscillator (VDPO). This is used as a base model oscillator for the analysis of the coupled oscillators. Hence, the three oscillators are approximated by the VDPO. From the nonlinear Van der Pol equations, the oscillators’ key parameters are obtained. It is analysed first the case without component mismatches and then the case with mismatches. The research is focused on determining the impact of the components’ mismatches on the oscillator key parameters: frequency, amplitude-, and quadrature-errors. Furthermore, the minimization of the errors by adjusting the circuit parameters is addressed. A novel quadrature RC-oscillator using capacitive coupling is proposed. The advantages of using the capacitive coupling are that it is noiseless, requires a small area, and has low power dissipation. The equations of the oscillation amplitude, frequency, quadrature-error, and amplitude mismatch are derived. The theoretical results are confirmed by simulation and by measurement of two prototypes fabricated in 130 nm standard complementary metal-oxide-semiconductor (CMOS) technology. The measurements reveal that the power increase due to the coupling is marginal, leading to a figure-of-merit of -154.8 dBc/Hz. These results are consistent with the noiseless feature of this coupling and are comparable to those of the best state-of-the-art RC-oscillators, in the GHz range, but with the lowest power consumption (about 9 mW). The results for the three oscillators show that the amplitude- and the quadrature-errors are proportional to the component mismatches and inversely proportional to the coupling strength. Thus, increasing the coupling strength decreases both the amplitude- and quadrature-errors. With proper coupling strength, a quadrature error below 1° and amplitude imbalance below 1% are obtained. Furthermore, the simulations show that increasing the coupling strength reduces the phase noise. Hence, there is no trade-off between phase noise and quadrature error. In the twointegrator oscillator study, it was found that the quadrature error can be eliminated by adjusting the transconductances to compensate the capacitance mismatch. However, to obtain outputs in perfect quadrature one must allow some amplitude error

Wireless-coupled oscillator systems with an injection-locking signal

A detailed analysis of wireless-coupled oscillator systems under the effect of an injection-locking signal is presented. The injection source of high spectral purity is introduced at a single node and enables a reduction of the phase-noise spectral density. Under this injection source, the behavior of the coupled system is qualitatively different from the one obtained in free-running conditions. Two cases are considered: bilateral synchronization, in which an independent source is connected to a particular system oscillator, coupled to the other oscillator elements, and unilateral synchronization, in which one of these elements is replaced by an independent source that cannot be influenced by the rest. The two cases are illustrated through the analysis of a wireless-coupled system with a star topology, such that the injection signal is introduced at the central node. The investigation involves an insightful analytical calculation of the coexisting steady-state solutions, as well as a determination of their stability and bifurcation properties and phase noise. The injection signal stabilizes the system in a large and continuous distance interval, enabling a more robust operation than in autonomous (noninjected) conditions. A coupled system operating at 2.45 GHz has been manufactured and experimentally characterized, obtaining a very good agreement between simulations and measurements.This work was supported by the Spanish Ministry of Economy and Competitiveness and the European Regional Development Fund (ERDF/FEDER) under research projects TEC2014-60283-C3-1-R and TEC2017-88242-C3-1-R

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

A low power, low noise, 1.8 GHz voltage-controlled oscillator

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (leaf 97).by Donald A. Hitko.M.S

Unified volterra series analysis of injection locked oscillators.

by Fan Chun-Wah.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 90-[91]).Abstract also in Chinese.Chapter CHAPTER 1: --- INTRODUCTION --- p.1Chapter CHAPTER 2: --- BACKGROUND OF INJECTION LOCKING --- p.3Chapter 2.1 --- Basics of Injection Locking --- p.3Chapter 2.2 --- Analytical Methods for Injection Locking --- p.6Chapter 2.2.1 --- Analysis of Fundamental Mode Injection Locking --- p.6Chapter 2.2.2 --- Analysis of Ha rmonic/Subharmonic Injection Locking --- p.9Chapter 2.4 --- Numerical Methods --- p.11Chapter CHAPTER 3: --- THE VOLTERRA SERIES METHOD FOR NONLINEAR CIRCUIT ANALYSIS --- p.13Chapter 3.1 --- Volterra Expansion --- p.14Chapter 3.2 --- Evaluation of Nonlinear Transfer Function --- p.16Chapter 3.2.1 --- Probing Method --- p.16Chapter 3.2.2 --- Nonlinear Current Method --- p.17Chapter 3.2.3 --- Higher order nonlinear current --- p.20Chapter 3.2.4 --- Voltage response by using nonlinear transfer function --- p.20Chapter 3.3 --- Advantage of Volterra Series --- p.21Chapter 3.4 --- Volterra Series Simulator(VSS) Implementation --- p.22Chapter 3.4.1 --- Admittance Matrix Formulation --- p.22Chapter 3.4.2 --- Evaluation of Nonlinear Response --- p.26Chapter 3.4.3 --- Local Cache and Global Cache --- p.26Chapter 3.4.4 --- Components Library --- p.27Chapter 3.4.5 --- Verification of Simulator --- p.27Chapter CHAPTER 4: --- VOLTERRA SERIES GENERAL INJECTION-LOCKED OSCILLATOR FORMULATION --- p.28Chapter 4.1 --- Volterra Series Approach to Analysis of Autonomous System --- p.29Chapter 4.1.1 --- Chua and Tang's work --- p.29Chapter 4.1.2 --- Cheng and Everard's work --- p.29Chapter 4.1.3 --- Huang and Chu 's work --- p.30Chapter 4.2 --- A Novel Approach --- p.33Chapter 4.3 --- Derivation of Determining Equation --- p.35Chapter 4.4 --- Injection Lock vector and circuit synthesis --- p.38Chapter 4.5 --- Modification to Volterra Series Simulator (VSS) --- p.40Chapter CHAPTER 5: --- CIRCUIT MODELING AND PARAMETER EXTRACTION --- p.42Chapter 5.1 --- Forward-Bias Gate Measurement --- p.42Chapter 5.2 --- Low FREQUENCY S-PARAMETER MEASUREMENT --- p.50Chapter 5.3 --- Parameter Extraction from High Frequency S-Parameter Data --- p.52Chapter 5.3.1 --- Direct Extraction Method --- p.52Chapter 5.3.2 --- Estimation of lead inductance --- p.56Chapter 5.4 --- Large Signal Characterization and Extraction --- p.59Chapter 5.4.1 --- Large Signal Model --- p.59Chapter 5.4.2 --- Extraction of g2 and g3 --- p.60Chapter 5.5 --- Equivalent circuit model for inductor and capacitor --- p.67Chapter CHAPTER 6: --- APPLICATION TO 1/3 ANALOG FREQUENCY DIVIDER --- p.68Chapter 6.1 --- Oscillator design by negative resistance approach --- p.68Chapter 6.2 --- Simulation of Free Running Oscillation by VSS --- p.73Chapter 6.3 --- Simulation of injection locked oscillator by VSS --- p.75Chapter 6.4 --- Injection Locking Experiment --- p.77Chapter 6.5 --- Injection Lock Vector --- p.80Chapter CHAPTER 7: --- CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK --- p.85Chapter 7.1 --- Conclusions --- p.85Chapter 7.2 --- Recommendations for Future Work --- p.86APPENDIX 1: REFERENCES --- p.87APPENDIX 2: PUBLICATION --- p.9