Circuit Techniques for Low-Power and Secure Internet-of-Things Systems

The coming of Internet of Things (IoT) is expected to connect the physical world to the cyber world through ubiquitous sensors, actuators and computers. The nature of these applications demand long battery life and strong data security. To connect billions of things in the world, the hardware platform for IoT systems must be optimized towards low power consumption, high energy efficiency and low cost. With these constraints, the security of IoT systems become a even more difficult problem compared to that of computer systems. A new holistic system design considering both hardware and software implementations is demanded to face these new challenges. In this work, highly robust and low-cost true random number generators (TRNGs) and physically unclonable functions (PUFs) are designed and implemented as security primitives for secret key management in IoT systems. They provide three critical functions for crypto systems including runtime secret key generation, secure key storage and lightweight device authentication. To achieve robustness and simplicity, the concept of frequency collapse in multi-mode oscillator is proposed, which can effectively amplify the desired random variable in CMOS devices (i.e. process variation or noise) and provide a runtime monitor of the output quality. A TRNG with self-tuning loop to achieve robust operation across -40 to 120 degree Celsius and 0.6 to 1V variations, a TRNG that can be fully synthesized with only standard cells and commercial placement and routing tools, and a PUF with runtime filtering to achieve robust authentication, are designed based upon this concept and verified in several CMOS technology nodes. In addition, a 2-transistor sub-threshold amplifier based "weak" PUF is also presented for chip identification and key storage. This PUF achieves state-of-the-art 1.65% native unstable bit, 1.5fJ per bit energy efficiency, and 3.16% flipping bits across -40 to 120 degree Celsius range at the same time, while occupying only 553 feature size square area in 180nm CMOS. Secondly, the potential security threats of hardware Trojan is investigated and a new Trojan attack using analog behavior of digital processors is proposed as the first stealthy and controllable fabrication-time hardware attack. Hardware Trojan is an emerging concern about globalization of semiconductor supply chain, which can result in catastrophic attacks that are extremely difficult to find and protect against. Hardware Trojans proposed in previous works are based on either design-time code injection to hardware description language or fabrication-time modification of processing steps. There have been defenses developed for both types of attacks. A third type of attack that combines the benefits of logical stealthy and controllability in design-time attacks and physical "invisibility" is proposed in this work that crosses the analog and digital domains. The attack eludes activation by a diverse set of benchmarks and evades known defenses. Lastly, in addition to security-related circuits, physical sensors are also studied as fundamental building blocks of IoT systems in this work. Temperature sensing is one of the most desired functions for a wide range of IoT applications. A sub-threshold oscillator based digital temperature sensor utilizing the exponential temperature dependence of sub-threshold current is proposed and implemented. In 180nm CMOS, it achieves 0.22/0.19K inaccuracy and 73mK noise-limited resolution with only 8865 square micrometer additional area and 75nW extra power consumption to an existing IoT system.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138779/1/kaiyuan_1.pd

Environment-Induced Decoherence and the Transition From Quantum to Classical

We study dynamics of quantum open systems, paying special attention to those aspects of their evolution which are relevant to the transition from quantum to classical. We begin with a discussion of the conditional dynamics of simple systems. The resulting models are straightforward but suffice to illustrate basic physical ideas behind quantum measurements and decoherence. To discuss decoherence and environment-induced superselection einselection in a more general setting, we sketch perturbative as well as exact derivations of several master equations valid for various systems. Using these equations we study einselection employing the general strategy of the predictability sieve. Assumptions that are usually made in the discussion of decoherence are critically reexamined along with the ``standard lore'' to which they lead. Restoration of quantum-classical correspondence in systems that are classically chaotic is discussed. The dynamical second law -it is shown- can be traced to the same phenomena that allow for the restoration of the correspondence principle in decohering chaotic systems (where it is otherwise lost on a very short time-scale). Quantum error correction is discussed as an example of an anti-decoherence strategy. Implications of decoherence and einselection for the interpretation of quantum theory are briefly pointed out.Comment: 80 pages, 7 figures included, Lectures given by both authors at the 72nd Les Houches Summer School on "Coherent Matter Waves", July-August 199

Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond

We present architectures, circuits, and algorithms for dynamic 3-D lensing and focusing of electromagnetic power in radiative near- and far-field regions by arrays that can be arbitrary and nonuniform. They can benefit applications such as wireless power transfer at a distance (WPT-AD), volumetric sensing and imaging, high-throughput communications, and optical phased arrays. Theoretical limits on system performance are calculated. An adaptive algorithm focuses the power at the receiver(s) without prior knowledge of its location(s). It uses orthogonal bases to change the phases of multiple elements simultaneously to enhance the dynamic range. One class of such 2-D orthogonal and pseudo-orthogonal masks is constructed using the Hadamard and pseudo-Hadamard matrices. Generation and recovery units (GU and RU) work collaboratively to focus energy quickly and reliably with no need for factory calibration. Orthogonality enables batch processing in high-latency and low-rate communication settings. Secondary vector-based calculations allow instantaneous refocusing at different locations using element-wise calculations. An emulator enables further evaluation of the system. We demonstrate modular WPT-AD GUs of up to 400 elements utilizing arrays of 65-nm CMOS ICs to focus power on RUs that convert the RF power to dc. Each RFIC synthesizes 16 independently phase-controlled RF outputs around 10 GHz from a common single low-frequency reference. Detailed measurements demonstrate the feasibility and effectiveness of RF lensing techniques presented in this article. More than 2 W of dc power can be recovered through a wireless transfer at distances greater than 1 m. The system can dynamically project power at various angles and at distances greater than 10 m. These developments are another step toward unified wireless power, sensing, and communication solutions in the future

Within-Die Delay Variation Measurement And Analysis For Emerging Technologies Using An Embedded Test Structure

Both random and systematic within-die process variations (PV) are growing more severe with shrinking geometries and increasing die size. Escalation in the variations in delay and power with reductions in feature size places higher demands on the accuracy of variation models. Their availability can be used to improve yield, and the corresponding profitability and product quality of the fabricated integrated circuits (ICs). Sources of within-die variations include optical source limitations, and layout-based systematic effects (pitch, line-width variability, and microscopic etch loading). Unfortunately, accurate models of within-die PVs are becoming more difficult to derive because of their increasingly sensitivity to design-context. Embedded test structures (ETS) continue to play an important role in the development of models of PVs and as a mechanism to improve correlations between hardware and models. Variations in path delays are increasing with scaling, and are increasingly affected by neighborhood\u27 interactions. In order to fully characterize within-die variations, delays must be measured in the context of actual core-logic macros. Doing so requires the use of an embedded test structure, as opposed to traditional scribe line test structures such as ring oscillators (RO). Accurate measurements of within-die variations can be used, e.g., to better tune models to actual hardware (model-to-hardware correlations). In this research project, I propose an embedded test structure called REBEL (Regional dELay BEhavior) that is designed to measure path delays in a minimally invasive fashion; and its architecture measures the path delays more accurately. Design for manufacture-ability (DFM) analysis is done on the on 90 nm ASIC chips and 28nm Zynq 7000 series FPGA boards. I present ASIC results on within-die path delay variations in a floating-point unit (FPU) fabricated in IBM\u27s 90 nm technology, with 5 pipeline stages, used as a test vehicle in chip experiments carried out at nine different temperature/voltage (TV) corners. Also experimental data has been analyzed for path delay variations in short vs long paths. FPGA results on within-die variation and die-to-die variations on Advanced Encryption System (AES) using single pipelined stage are also presented. Other analysis that have been performed on the calibrated path delays are Flip Flop propagation delays for both rising and falling edge (tpHL and tpLH), uncertainty analysis, path distribution analysis, short versus long path variations and mid-length path within-die variation. I also analyze the impact on delay when the chips are subjected to industrial-level temperature and voltage variations. From the experimental results, it has been established that the proposed REBEL provides capabilities similar to an off-chip logic analyzer, i.e., it is able to capture the temporal behavior of the signal over time, including any static and dynamic hazards that may occur on the tested path. The ASIC results further show that path delays are correlated to the launch-capture (LC) interval used to time them. Therefore, calibration as proposed in this work must be carried out in order to obtain an accurate analysis of within-die variations. Results on ASIC chips show that short paths can vary up to 35% on average, while long paths vary up to 20% at nominal temperature and voltage. A similar trend occurs for within-die variations of mid-length paths where magnitudes reduced to 20% and 5%, respectively. The magnitude of delay variations in both these analyses increase as temperature and voltage are changed to increase performance. The high level of within-die delay variations are undesirable from a design perspective, but they represent a rich source of entropy for applications that make use of \u27secrets\u27 such as authentication, hardware metering and encryption. Physical unclonable functions (PUFs) are a class of primitives that leverage within-die-variations as a means of generating random bit strings for these types of applications, including hardware security and trust. Zynq FPGAs Die-to-Die and within-die variation study shows that on average there is 5% of within-Die variation and the range of die-to-Die variation can go upto 3ns. The die-to-Die variations can be explored in much further detail to study the variations spatial dependance. Additionally, I also carried out research in the area data mining to cater for big data by focusing the work on decision tree classification (DTC) to speed-up the classification step in hardware implementation. For this purpose, I devised a pipelined architecture for the implementation of axis parallel binary decision tree classification for meeting up with the requirements of execution time and minimal resource usage in terms of area. The motivation for this work is that analyzing larger data-sets have created abundant opportunities for algorithmic and architectural developments, and data-mining innovations, thus creating a great demand for faster execution of these algorithms, leading towards improving execution time and resource utilization. Decision trees (DT) have since been implemented in software programs. Though, the software implementation of DTC is highly accurate, the execution times and the resource utilization still require improvement to meet the computational demands in the ever growing industry. On the other hand, hardware implementation of DT has not been thoroughly investigated or reported in detail. Therefore, I propose a hardware acceleration of pipelined architecture that incorporates the parallel approach in acquiring the data by having parallel engines working on different partitions of data independently. Also, each engine is processing the data in a pipelined fashion to utilize the resources more efficiently and reduce the time for processing all the data records/tuples. Experimental results show that our proposed hardware acceleration of classification algorithms has increased throughput, by reducing the number of clock cycles required to process the data and generate the results, and it requires minimal resources hence it is area efficient. This architecture also enables algorithms to scale with increasingly large and complex data sets. We developed the DTC algorithm in detail and explored techniques for adapting it to a hardware implementation successfully. This system is 3.5 times faster than the existing hardware implementation of classification.\u2

Balancing expectations:Adaptive flexibility in mammalian circadian rhythms

Circadian rhythms are internally generated oscillations of approximately 24 hours that synchronize with the environments day-night cycle, which drive and modulate countless behavioural and physiological processes. In this thesis we use a novel behavioural work-for-food paradigm which allows to study how changes in energy balance cause a change in the temporal niche of mice, making them adopt a day-active activity pattern. We show and discuss data supporting a functional role of circadian flexibility; diurnal activity patterns requiring less energy versus remaining night-active - for burrowing small mammals in temperate climate. We build on this by showing the rearrangements in temporal niche are associated with plasticity in the direct light response (photic masking) and explore differences between male and female mice. Further we show data that neither the adrenals nor the Paraventricular thalamic Nucleus are essential for circadian niche adaptation whereas the central circadian clock located in the suprachiasmatic nucleus remains of vital importance, despite itself not appearing to change phase. The rigidity of the SCN-timing might be linked to its role in measuring daylength and guiding seasonal rhythms. Which processes make behavioural and physiological rhythms obtain a different phase angle to the SCN during simulated food shortage remains largely elusive. The work in this thesis provides a solid scientific basis to re-address circadian flexibility and it’s relation to energy balance in future studies. Gaining more insights in circadian rhythm flexibility might solve the poorly understood mechanisms behind metabolic risks associated with human shift-work and how to cope with circadian disruptions

Distributed EaaS simulation using TEEs: A case study in the implementation and practical application of an embedded computer cluster

Internet of Things (IoT) devices with limited resources struggle to generate the high-quality entropy required for high-quality randomness. This results in weak cryptographic keys. As keys are a single point of failure in modern cryptography, IoT devices performing cryptographic operations may be susceptible to a variety of attacks. To address this issue, we develop an Entropy as a Service (EaaS) simulation. The purpose of EaaS is to provide IoT devices with high-quality entropy as a service so that they can use it to generate strong keys. Additionally, we utilise Trusted Execution Environments (TEEs) in the simulation. TEE is a secure processor component that provides data protection, integrity, and confidentiality for select applications running on the processor by isolating them from other system processes (including the OS). TEE thereby enhances system security. The EaaS simulation is performed on a computer cluster known as the Magi cluster. Magi cluster is a private computer cluster that has been designed, built, configured, and tested as part of this thesis to meet the requirements of Tampere University's Network and Information Security Group (NISEC). In this thesis, we explain how the Magi cluster is implemented and how it is utilised to conduct a distributed EaaS simulation utilising TEEs.Esineiden internetin (Internet of Things, IoT) laitteilla on tyypillisesti rajallisten resurssien vuoksi haasteita tuottaa tarpeeksi korkealaatuista entropiaa vahvan satunnaisuuden luomiseen. Tämä johtaa heikkoihin salausavaimiin. Koska salausavaimet ovat modernin kryptografian heikoin lenkki, IoT-laitteilla tehtävät kryptografiset operaatiot saattavat olla haavoittuvaisia useita erilaisia hyökkäyksiä vastaan. Ratkaistaksemme tämän ongelman kehitämme simulaation, joka tarjoaa IoT-laitteille vahvaa entropiaa palveluna (Entropy as a Service, EaaS). EaaS-simulaation ideana on jakaa korkealaatuista entropiaa palveluna IoT-laitteille, jotta ne pystyvät luomaan vahvoja salausavaimia. Hyödynnämme simulaatiossa lisäksi luotettuja suoritusympäristöjä (Trusted Execution Environment, TEE). TEE on prosessorilla oleva erillinen komponentti, joka tarjoaa eristetyn ja turvallisen ajoympäristön valituille ohjelmille. TEE:tä hyödyntämällä ajonaikaiselle ohjelmalle voidaan taata datan suojaus, luottamuksellisuus sekä eheys eristämällä se muista järjestelmällä ajetuista ohjelmista (mukaan lukien käyttöjärjestelmä). Näin ollen TEE parantaa järjestelmän tietoturvallisuutta. EaaS-simulaatio toteutetaan Magi-nimisellä tietokoneklusterilla. Magi on Tampereen Yliopiston Network and Information Security Group (NISEC) -tutkimusryhmän oma yksityinen klusteri, joka on suunniteltu, rakennettu, määritelty ja testattu osana tätä diplomityötä. Tässä diplomityössä käymme läpi, kuinka Magi-klusteri on toteutettu ja kuinka sillä toteutetaan hajautettu EaaS-simulaatio hyödyntäen TEE:itä

Proceedings of the Workshop on the Scientific Applications of Clocks in Space

The Workshop on Scientific Applications of Clocks in space was held to bring together scientists and technologists interested in applications of ultrastable clocks for test of fundamental theories, and for other science investigations. Time and frequency are the most precisely determined of all physical parameters, and thus are the required tools for performing the most sensitive tests of physical theories. Space affords the opportunity to make measurement, parameters inaccessible on Earth, and enables some of the most original and sensitive tests of fundamental theories. In the past few years, new developments in clock technologies have pointed to the opportunity for flying ultrastable clocks in support of science investigations of space missions. This development coincides with the new NASA paradigm for space flights, which relies on frequent, low-cost missions in place of the traditional infrequent and high-cost missions. The heightened interest in clocks in space is further advanced by new theoretical developments in various fields. For example, recent developments in certain Grand Unified Theory formalisms have vastly increased interest in fundamental tests of gravitation physics with clocks. The workshop included sessions on all related science including relativity and gravitational physics, cosmology, orbital dynamics, radio science, geodynamics, and GPS science and others, as well as a session on advanced clock technology