28 research outputs found

    Search for the TTH Production in Multi-Leptonic Final States with the Atlas Detector at LHC

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    Since the discovery of the Higgs boson in 2012, the aim of the correlated physics analyses moved towards the measurement of its properties to verify the consistence with the Standard Model and to study possible signals of physics Beyond Standard Model. In particular, any discrepancy in the Higgs-SM couplings would point to new physics contributions. The ttH channels is a privileged channel for this pourpose, because it depends on a small number of BSM parameters. In this thesis the analysis of the production of a Higgs boson in association with a top and anti-top quark couple and decay into multi-leptonic final states in ATLAS at LHC is described. The analysis is focused on the channel defined by two light leptons of the same sign and no hadronic tau leptons in both Run I and Run II. The analysis is an essential preparatory step for the 2016 data-taking. After introducing the Higgs boson, LHC and the ATLAS experiment, the results of the Run I analysis are presented, which pose a first limit on the deviation of the cross section from the SM. A large part of the thesis is dedicated to the data-driven estimation of the main background of this channel, fake leptons produced in meson decays, using a technique denominated matrix method. This alternative background estimation is explained and applied to the analysis, producing alternative results. In the last part of the thesis, the first stages of the analysis of the 2015 data is shown, in preparation of the 2016 data-taking

    2013 IMSAloquium, Student Investigation Showcase

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    This year, we are proudly celebrating the twenty-fifth anniversary of IMSA’s Student Inquiry and Research (SIR) Program. Our first IMSAloquium, then called Presentation Day, was held in 1989 with only ten presentations; this year we are nearing two hundred.https://digitalcommons.imsa.edu/archives_sir/1005/thumbnail.jp

    Just-in-time Hardware generation for abstracted reconfigurable computing

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    This thesis addresses the use of reconfigurable hardware in computing platforms, in order to harness the performance benefits of dedicated hardware whilst maintaining the flexibility associated with software. Although the reconfigurable computing concept is not new, the low level nature of the supporting tools normally used, together with the consequent limited level of abstraction and resultant lack of backwards compatibility, has prevented the widespread adoption of this technology. In addition, bandwidth and architectural limitations, have seriously constrained the potential improvements in performance. A review of existing approaches and tools flows is conducted to highlight the current problems being faced in this field. The objective of the work presented in this thesis is to introduce a radically new approach to reconfigurable computing tool flows. The runtime based tool flow introduces complete abstraction between the application developer and the underlying hardware. This new technique eliminates the ease of use and backwards compatibility issues that have plagued the reconfigurable computing concept, and could pave the way for viable mainstream reconfigurable computing platforms. An easy to use, cycle accurate behavioural modelling system is also presented, which was used extensively during the early exploration of new concepts and architectures. Some performance improvements produced by the new reconfigurable computing tool flow, when applied to both a MIPS based embedded platform, and the Cray XDl, are also presented. These results are then analyzed and the hardware and software factors affecting the performance increases that were obtained are discussed, together with potential techniques that could be used to further increase the performance of the system. Lastly a heterogenous computing concept is proposed, in which, a computer system, containing multiple types of computational resource is envisaged, each having their own strengths and weaknesses (e.g. DSPs, CPUs, FPGAs). A revolutionary new method of fully exploiting the potential of such a system, whilst maintaining scalability, backwards compatibility, and ease of use is also presented

    Stream ciphers for secure display

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    In any situation where private, proprietary or highly confidential material is being dealt with, the need to consider aspects of data security has grown ever more important. It is usual to secure such data from its source, over networks and on to the intended recipient. However, data security considerations typically stop at the recipient's processor, leaving connections to a display transmitting raw data which is increasingly in a digital format and of value to an adversary. With a progression to wireless display technologies the prominence of this vulnerability is set to rise, making the implementation of 'secure display' increasingly desirable. Secure display takes aspects of data security right to the display panel itself, potentially minimising the cost, component count and thickness of the final product. Recent developments in display technologies should help make this integration possible. However, the processing of large quantities of time-sensitive data presents a significant challenge in such resource constrained environments. Efficient high- throughput decryption is a crucial aspect of the implementation of secure display and one for which the widely used and well understood block cipher may not be best suited. Stream ciphers present a promising alternative and a number of strong candidate algorithms potentially offer the hardware speed and efficiency required. In the past, similar stream ciphers have suffered from algorithmic vulnerabilities. Although these new-generation designs have done much to respond to this concern, the relatively short 80-bit key lengths of some proposed hardware candidates, when combined with ever-advancing computational power, leads to the thesis identifying exhaustive search of key space as a potential attack vector. To determine the value of protection afforded by such short key lengths a unique hardware key search engine for stream ciphers is developed that makes use of an appropriate data element to improve search efficiency. The simulations from this system indicate that the proposed key lengths may be insufficient for applications where data is of long-term or high value. It is suggested that for the concept of secure display to be accepted, a longer key length should be used

    Undergraduate and Graduate Course Descriptions, 2013 Summer

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    Wright State University undergraduate and graduate course descriptions from Summer 2013

    Undergraduate and Graduate Course Descriptions, 2013 Summer

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    Wright State University undergraduate and graduate course descriptions from Summer 2013

    Undergraduate and Graduate Course Descriptions, 2016 Fall

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    Wright State University undergraduate and graduate course descriptions from Fall 2016

    Undergraduate and Graduate Course Descriptions, 2017 Fall

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    Wright State University undergraduate and graduate course descriptions from Fall 2017

    Undergraduate and Graduate Course Descriptions, 2017 Spring

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    Wright State University undergraduate and graduate course descriptions from Spring 2017
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