29 research outputs found
Π‘Ρ Π΅ΠΌΠ° ΠΊΠΎΡΡΠ΅ΠΊΡΠΈΠΈ ΡΠΈΠ³Π½Π°Π»ΠΎΠ² Π΄Π»Ρ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΡ ΡΡΡΡΠΎΠΉΡΡΠ² Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠΊΠΈ Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π΄ΠΎΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Ρ ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΌ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ ΠΏΠΎ ΠΏΠ°ΡΠΈΡΠ΅ΡΡ
Simpler than known structure of the system with error correction in calculations is proposed based on duplication and triplication of blocks with majority principle of choosing the values of signals. It is advisable to use the new fault-tolerant structure for automation devices with combinational logic. In fault-tolerant structure synthesis, the parity method is used to establish the fact of a fault in the main logic unit and the logical complement method is used determine incorrectly calculated output functions and to generate signals for their correction. The method also allows to adjust the values of incorrectly calculated functions. Structural diagram and description of error correction system are given. The synthesis algorithm of control equipment is described with minimization of the technical implementation complexity. The experiment results with control combinational circuits are given, confirming the high efficiency of proposed system structure with error correction.ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π° Π±ΠΎΠ»Π΅Π΅ ΠΏΡΠΎΡΡΠ°Ρ ΡΡΡΡΠΊΡΡΡΠ° ΡΠΈΡΡΠ΅ΠΌΡ Ρ ΠΊΠΎΡΡΠ΅ΠΊΡΠΈΠ΅ΠΉ ΠΎΡΠΈΠ±ΠΎΠΊ Π² Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΡΡ
, ΡΠ΅ΠΌ ΠΈΠ·Π²Π΅ΡΡΠ½ΡΠ΅ ΡΡΡΡΠΊΡΡΡΡ, ΠΎΡΠ½ΠΎΠ²Π°Π½Π½ΡΠ΅ Π½Π° Π΄ΡΠ±Π»ΠΈΡΠΎΠ²Π°Π½ΠΈΠΈ ΠΈ ΡΡΠΎΠΈΡΠΎΠ²Π°Π½ΠΈΠΈ Π±Π»ΠΎΠΊΠΎΠ² Ρ ΠΌΠ°ΠΆΠΎΡΠΈΡΠ°ΡΠ½ΡΠΌ ΠΏΡΠΈΠ½ΡΠΈΠΏΠΎΠΌ Π²ΡΠ±ΠΎΡΠ° Π·Π½Π°ΡΠ΅Π½ΠΈΠΉ ΡΠΈΠ³Π½Π°Π»ΠΎΠ². ΠΠΎΠ²ΡΡ ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΡΡ ΡΡΡΡΠΊΡΡΡΡ ΡΠ΅Π»Π΅ΡΠΎΠΎΠ±ΡΠ°Π·Π½ΠΎ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°ΡΡ Π΄Π»Ρ ΡΡΡΡΠΎΠΉΡΡΠ² Π°Π²ΡΠΎΠΌΠ°ΡΠΈΠΊΠΈ Ρ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΠΎΠΉ Π»ΠΎΠ³ΠΈΠΊΠΎΠΉ. ΠΡΠΈ ΡΠΈΠ½ΡΠ΅Π·Π΅ ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΠΎΠΉ ΡΡΡΡΠΊΡΡΡΡ ΠΏΡΠΈΠΌΠ΅Π½ΡΠ΅ΡΡΡ ΠΌΠ΅ΡΠΎΠ΄ ΠΏΠ°ΡΠΈΡΠ΅ΡΠ° Π΄Π»Ρ ΡΡΡΠ°Π½ΠΎΠ²Π»Π΅Π½ΠΈΡ ΡΠ°ΠΊΡΠ° Π²ΠΎΠ·Π½ΠΈΠΊΠ½ΠΎΠ²Π΅Π½ΠΈΡ Π½Π΅ΠΈΡΠΏΡΠ°Π²Π½ΠΎΡΡΠΈ Π² ΠΊΠΎΠ½ΡΡΠΎΠ»ΠΈΡΡΠ΅ΠΌΠΎΠΌ ΠΎΠ±ΡΠ΅ΠΊΡΠ΅ ΠΈ ΠΌΠ΅ΡΠΎΠ΄ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π΄ΠΎΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Π΄Π»Ρ ΠΎΠΏΡΠ΅Π΄Π΅Π»Π΅Π½ΠΈΡ Π½Π΅ΠΏΡΠ°Π²ΠΈΠ»ΡΠ½ΠΎ Π²ΡΡΠΈΡΠ»Π΅Π½Π½ΡΡ
Π²ΡΡ
ΠΎΠ΄Π½ΡΡ
ΡΡΠ½ΠΊΡΠΈΠΉ ΠΈ ΡΠΎΡΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΡΠΈΠ³Π½Π°Π»ΠΎΠ² Π΄Π»Ρ ΠΈΡ
ΠΊΠΎΡΡΠ΅ΠΊΡΠΈΠΈ. ΠΡΠΈΠ²Π΅Π΄Π΅Π½Π° ΡΡΡΡΠΊΡΡΡΠ½Π°Ρ ΡΡ
Π΅ΠΌΠ° ΡΠΈΡΡΠ΅ΠΌΡ Ρ ΠΊΠΎΡΡΠ΅ΠΊΡΠΈΠ΅ΠΉ ΠΎΡΠΈΠ±ΠΎΠΊ ΠΈ Π΄Π°Π½ΠΎ Π΅Π΅ ΠΎΠΏΠΈΡΠ°Π½ΠΈΠ΅. ΠΡΠ΅Π΄ΡΡΠ°Π²Π»Π΅Π½ Π°Π»Π³ΠΎΡΠΈΡΠΌ ΡΠΈΠ½ΡΠ΅Π·Π° ΠΊΠΎΠ½ΡΡΠΎΠ»ΡΠ½ΠΎΠ³ΠΎ ΠΎΠ±ΠΎΡΡΠ΄ΠΎΠ²Π°Π½ΠΈΡ Ρ ΠΌΠΈΠ½ΠΈΠΌΠΈΠ·Π°ΡΠΈΠ΅ΠΉ ΡΠ»ΠΎΠΆΠ½ΠΎΡΡΠΈ Π΅Π³ΠΎ ΡΠ΅Ρ
Π½ΠΈΡΠ΅ΡΠΊΠΎΠΉ ΡΠ΅Π°Π»ΠΈΠ·Π°ΡΠΈΠΈ. Π Π΅Π·ΡΠ»ΡΡΠ°ΡΡ ΡΠΊΡΠΏΠ΅ΡΠΈΠΌΠ΅Π½ΡΠΎΠ² Ρ ΠΊΠΎΠ½ΡΡΠΎΠ»ΡΠ½ΡΠΌΠΈ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΠΌΠΈ ΡΡ
Π΅ΠΌΠ°ΠΌΠΈ ΠΏΠΎΠ΄ΡΠ²Π΅ΡΠΆΠ΄Π°ΡΡ Π²ΡΡΠΎΠΊΡΡ ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΡ ΠΏΡΠΈΠΌΠ΅Π½Π΅Π½ΠΈΡ ΠΏΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Π½ΠΎΠΉ ΡΡΡΡΠΊΡΡΡΡ ΡΠΈΡΡΠ΅ΠΌΡ Ρ ΠΊΠΎΡΡΠ΅ΠΊΡΠΈΠ΅ΠΉ ΠΎΡΠΈΠ±ΠΎΠΊ
Error correction circuits structures based on Boolean complement with calculation checking by code with summation of weighted transitions from bit to bit
ΠΡΠ΅Π΄Π»ΠΎΠΆΠ΅Π½Ρ Π½ΠΎΠ²ΡΠ΅ ΡΡΡΡΠΊΡΡΡΡ ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΡΡ
ΡΠΈΡΡΠΎΠ²ΡΡ
Π²ΡΡΠΈΡΠ»ΠΈΡΠ΅Π»ΡΠ½ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΈ ΡΠΈΡΡΠ΅ΠΌ, Π² ΠΎΡΠ½ΠΎΠ²Π΅ ΠΊΠΎΡΠΎΡΡΡ
Π»Π΅ΠΆΠΈΡ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ ΠΏΡΠΈΠ½ΡΠΈΠΏΠ° Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π΄ΠΎΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Π΄Π»Ρ ΡΠΈΠΊΡΠ°ΡΠΈΠΈ ΠΈΡΠΊΠ°ΠΆΠ΅Π½Π½ΡΡ
ΡΠΈΠ³Π½Π°Π»ΠΎΠ² ΠΈ ΡΡ
Π΅ΠΌ Π²ΡΡΡΠΎΠ΅Π½Π½ΠΎΠ³ΠΎ ΠΊΠΎΠ½ΡΡΠΎΠ»Ρ. ΠΠΎΡΠ»Π΅Π΄Π½ΠΈΠ΅ ΡΠ΅Π°Π»ΠΈΠ·ΡΡΡΡΡ Ρ ΠΏΡΠΈΠΌΠ΅Π½Π΅Π½ΠΈΠ΅ΠΌ ΠΊΠΎΠ΄Π° Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ Π²Π·Π²Π΅ΡΠ΅Π½Π½ΡΡ
ΠΏΠ΅ΡΠ΅Ρ
ΠΎΠ΄ΠΎΠ² ΠΎΡ ΡΠ°Π·ΡΡΠ΄Π° ΠΊ ΡΠ°Π·ΡΡΠ΄Ρ Π² ΠΈΠ½ΡΠΎΡΠΌΠ°ΡΠΈΠΎΠ½Π½ΠΎΠΌ Π²Π΅ΠΊΡΠΎΡΠ΅, ΠΏΡΠΈ ΠΏΠΎΡΡΡΠΎΠ΅Π½ΠΈΠΈ ΠΊΠΎΡΠΎΡΠΎΠ³ΠΎ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½Π° ΠΏΠΎΡΠ»Π΅Π΄ΠΎΠ²Π°ΡΠ΅Π»ΡΠ½ΠΎΡΡΡ Π²Π΅ΡΠΎΠ²ΡΡ
ΠΊΠΎΡΡΡΠΈΡΠΈΠ΅Π½ΡΠΎΠ², ΠΎΠ±ΡΠ°Π·ΡΡΡΠ°Ρ ΡΡΠ΄ Π²ΠΎΠ·ΡΠ°ΡΡΠ°ΡΡΠΈΡ
ΡΡΠ΅ΠΏΠ΅Π½Π΅ΠΉ ΡΠΈΡΠ»Π° 2. ΠΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ Π΄Π°Π½Π½ΠΎΠ³ΠΎ ΠΊΠΎΠ΄Π° Ρ ΡΡΠΌΠΌΠΈΡΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ ΠΏΠΎΠ·Π²ΠΎΠ»ΡΠ΅Ρ ΠΎΠ±Π½Π°ΡΡΠΆΠΈΠ²Π°ΡΡ Π»ΡΠ±ΡΠ΅ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΈ ΠΈΡΠΊΠ°ΠΆΠ΅Π½ΠΈΠΉ Π½Π° Π²ΡΡ
ΠΎΠ΄Π°Ρ
ΠΎΠ±ΡΠ΅ΠΊΡΠ° Π΄ΠΈΠ°Π³Π½ΠΎΡΡΠΈΡΠΎΠ²Π°Π½ΠΈΡ, Π·Π° ΠΈΡΠΊΠ»ΡΡΠ΅Π½ΠΈΠ΅ΠΌ ΠΎΠ΄Π½ΠΎΠ²ΡΠ΅ΠΌΠ΅Π½Π½ΠΎΠ³ΠΎ ΠΈΡΠΊΠ°ΠΆΠ΅Π½ΠΈΡ Π²ΡΠ΅Ρ
Π²ΡΡ
ΠΎΠ΄ΠΎΠ², ΡΡΠΎ Π½Π° ΠΏΡΠ°ΠΊΡΠΈΠΊΠ΅ Π±ΡΠ²Π°Π΅Ρ Π΄ΠΎΡΡΠ°ΡΠΎΡΠ½ΠΎ ΡΠ΅Π΄ΠΊΠΎ. ΠΠ°Π½ΠΎ ΠΎΠΏΠΈΡΠ°Π½ΠΈΠ΅ ΡΠ΅ΡΡΡΠ΅Ρ
ΡΡΡΡΠΊΡΡΡ: ΡΡΡΡΠΊΡΡΡΡ Ρ Π΄Π²ΠΎΠΉΠ½ΠΎΠΉ ΠΌΠΎΠ΄ΡΠ»ΡΠ½ΠΎΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΡΡ ΠΈ ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΌ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ ΠΎΡΠ½ΠΎΠ²Π½ΡΠΌ Π±Π»ΠΎΠΊΠΎΠΌ ΠΏΠΎ Π²ΡΠ±ΡΠ°Π½Π½ΠΎΠΌΡ ΠΊΠΎΠ΄Ρ, ΡΡΡΡΠΊΡΡΡΡ Ρ Π΄Π²ΠΎΠΉΠ½ΠΎΠΉ ΠΌΠΎΠ΄ΡΠ»ΡΠ½ΠΎΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΡΡ ΠΈ ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΌ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ ΡΠ΅Π·Π΅ΡΠ²Π½ΡΠΌ Π±Π»ΠΎΠΊΠΎΠΌ ΠΏΠΎ Π²ΡΠ±ΡΠ°Π½Π½ΠΎΠΌΡ ΠΊΠΎΠ΄Ρ, ΡΡΡΡΠΊΡΡΡΡ Ρ ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΌ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ ΠΎΡΠ½ΠΎΠ²Π½ΡΠΌ Π±Π»ΠΎΠΊΠΎΠΌ ΠΏΠΎ Π²ΡΠ±ΡΠ°Π½Π½ΠΎΠΌΡ ΠΊΠΎΠ΄Ρ ΠΈ Π±Π»ΠΎΠΊΠΎΠΌ ΡΠΈΠΊΡΠ°ΡΠΈΠΈ ΠΈΡΠΊΠ°ΠΆΠ΅Π½Π½ΡΡ
ΡΠΈΠ³Π½Π°Π»ΠΎΠ² Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π΄ΠΎΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ, ΡΡΡΡΠΊΡΡΡΡ Ρ Π±Π»ΠΎΠΊΠΎΠΌ ΡΠΈΠΊΡΠ°ΡΠΈΠΈ ΠΈΡΠΊΠ°ΠΆΠ΅Π½Π½ΡΡ
ΡΠΈΠ³Π½Π°Π»ΠΎΠ² Π½Π° ΠΎΡΠ½ΠΎΠ²Π΅ Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π΄ΠΎΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ Ρ Π½Π΅ΠΏΠΎΡΡΠ΅Π΄ΡΡΠ²Π΅Π½Π½ΡΠΌ ΠΊΠΎΠ½ΡΡΠΎΠ»Π΅ΠΌ Π²ΡΡΠΈΡΠ»Π΅Π½ΠΈΠΉ Π΄Π°Π½Π½ΡΠΌ Π±Π»ΠΎΠΊΠΎΠΌ. ΠΡΠΈΠ²ΠΎΠ΄ΡΡΡΡ ΠΏΡΠΈΠΌΠ΅ΡΡ ΡΠΈΠ½ΡΠ΅Π·Π° ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΈ Π΄Π°Π½Π° ΠΎΡΠ΅Π½ΠΊΠ° ΠΈΡ
ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΠΈ ΠΏΠΎ ΡΡΠ°Π²Π½Π΅Π½ΠΈΡ Ρ ΠΈΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ΠΌ ΡΡΠ°Π΄ΠΈΡΠΈΠΎΠ½Π½ΠΎΠΉ ΡΡΡΡΠΊΡΡΡΡ ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΡΡ
ΡΡΡΡΠΎΠΉΡΡΠ² ΠΈ ΡΠΈΡΡΠ΅ΠΌ, ΠΎΡΠ½ΠΎΠ²Π°Π½Π½ΠΎΠΉ Π½Π° ΡΡΠΎΠΉΠ½ΠΎΠΉ ΠΌΠΎΠ΄ΡΠ»ΡΠ½ΠΎΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΠΈ Ρ ΠΌΠ°ΠΆΠΎΡΠΈΡΠ°ΡΠ½ΠΎΠΉ ΠΊΠΎΡΡΠ΅ΠΊΡΠΈΠ΅ΠΉ ΡΠΈΠ³Π½Π°Π»ΠΎΠ². ΠΡΠ²Π΅ΡΠ΅Π½Ρ ΡΠ΅Π·ΡΠ»ΡΡΠ°ΡΡ ΡΠΊΡΠΏΠ΅ΡΠΈΠΌΠ΅Π½ΡΠΎΠ² Ρ ΠΊΠΎΠ½ΡΡΠΎΠ»ΡΠ½ΡΠΌΠΈ ΠΊΠΎΠΌΠ±ΠΈΠ½Π°ΡΠΈΠΎΠ½Π½ΡΠΌΠΈ ΡΡ
Π΅ΠΌΠ°ΠΌΠΈ LGβ93 ΠΈ MCNC Benchmarks, ΡΠ°ΠΊΠΆΠ΅ ΠΏΠΎΠΊΠ°Π·Π°Π²ΡΠΈΠ΅ ΡΡΡΠ΅ΠΊΡΠΈΠ²Π½ΠΎΡΡΡ ΠΏΡΠ΅Π΄Π»Π°Π³Π°Π΅ΠΌΡΡ
ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΡΡ
ΡΡΡΡΠΊΡΡΡ. ΠΡΠΏΠΎΠ»ΡΠ·ΠΎΠ²Π°Π½ΠΈΠ΅ ΠΏΡΠΈΠ½ΡΠΈΠΏΠ° Π»ΠΎΠ³ΠΈΡΠ΅ΡΠΊΠΎΠ³ΠΎ Π΄ΠΎΠΏΠΎΠ»Π½Π΅Π½ΠΈΡ ΠΏΠΎΠ·Π²ΠΎΠ»ΡΠ΅Ρ ΡΠΈΠ½ΡΠ΅Π·ΠΈΡΠΎΠ²Π°ΡΡ ΠΎΡΠΊΠ°Π·ΠΎΡΡΡΠΎΠΉΡΠΈΠ²ΡΠ΅ ΡΠΈΡΡΠΎΠ²ΡΠ΅ ΡΡΡΡΠΎΠΉΡΡΠ²Π° ΠΈ ΡΠΈΡΡΠ΅ΠΌΡ, Π² ΠΊΠΎΡΠΎΡΡΡ
Π½Π΅ ΡΡΠ΅Π±ΡΠ΅ΡΡΡ ΠΏΡΡΠΌΠΎΠ³ΠΎ ΡΠ΅Π·Π΅ΡΠ²ΠΈΡΠΎΠ²Π°Π½ΠΈΡ ΠΈ Π²Π½Π΅ΡΠ΅Π½ΠΈΡ ΠΌΠΎΠ΄ΡΠ»ΡΠ½ΠΎΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΠΈ, ΡΡΠΎ Π½Π° ΠΏΡΠ°ΠΊΡΠΈΠΊΠ΅ ΠΌΠΎΠΆΠ΅Ρ Π΄Π°Π²Π°ΡΡ ΡΡΡΠ΅ΡΡΠ²Π΅Π½Π½ΠΎΠ΅ ΡΠ½ΠΈΠΆΠ΅Π½ΠΈΠ΅ ΡΡΡΡΠΊΡΡΡΠ½ΠΎΠΉ ΠΈΠ·Π±ΡΡΠΎΡΠ½ΠΎΡΡΠΈ ΠΊΠΎΠ½Π΅ΡΠ½ΠΎΠ³ΠΎ ΠΎΠ±ΡΠ΅ΠΊΡΠ°
Behind the Last Line of Defense -- Surviving SoC Faults and Intrusions
Today, leveraging the enormous modular power, diversity and flexibility of manycore systems-on-a-chip (SoCs) requires careful orchestration of complex resources, a task left to low-level software, e.g. hypervisors. In current architectures, this software forms a single point of failure and worthwhile target for attacks: once compromised, adversaries gain access to all information and full control over the platform and the environment it controls. This paper proposes Midir, an enhanced manycore architecture, effecting a paradigm shift from SoCs to distributed SoCs. Midir changes the way platform resources are controlled, by retrofitting tile-based fault containment through well known mechanisms, while securing low-overhead quorum-based consensus on all critical operations, in particular privilege management and, thus, management of containment domains. Allowing versatile redundancy management, Midir promotes resilience for all software levels, including at low level. We explain this architecture, its associated algorithms and hardware mechanisms and show, for the example of a Byzantine fault tolerant microhypervisor, that it outperforms the highly efficient MinBFT by one order of magnitude
Behind the Last Line of Defense -- Surviving SoC Faults and Intrusions
Today, leveraging the enormous modular power, diversity and flexibility of
manycore systems-on-a-chip (SoCs) requires careful orchestration of complex
resources, a task left to low-level software, e.g. hypervisors. In current
architectures, this software forms a single point of failure and worthwhile
target for attacks: once compromised, adversaries gain access to all
information and full control over the platform and the environment it controls.
This paper proposes Midir, an enhanced manycore architecture, effecting a
paradigm shift from SoCs to distributed SoCs. Midir changes the way platform
resources are controlled, by retrofitting tile-based fault containment through
well known mechanisms, while securing low-overhead quorum-based consensus on
all critical operations, in particular privilege management and, thus,
management of containment domains. Allowing versatile redundancy management,
Midir promotes resilience for all software levels, including at low level. We
explain this architecture, its associated algorithms and hardware mechanisms
and show, for the example of a Byzantine fault tolerant microhypervisor, that
it outperforms the highly efficient MinBFT by one order of magnitude
Operating System Support for Redundant Multithreading
Failing hardware is a fact and trends in microprocessor design indicate that the fraction of hardware suffering from permanent and transient faults will continue to increase in future chip generations. Researchers proposed various solutions to this issue with different downsides: Specialized hardware components make hardware more expensive in production and consume additional energy at runtime. Fault-tolerant algorithms and libraries enforce specific programming models on the developer. Compiler-based fault tolerance requires the source code for all applications to be available for recompilation. In this thesis I present ASTEROID, an operating system architecture that integrates applications with different reliability needs.
ASTEROID is built on top of the L4/Fiasco.OC microkernel and extends the system with Romain, an operating system service that transparently replicates user applications. Romain supports single- and multi-threaded applications without requiring access to the application's source code. Romain replicates applications and their resources completely and thereby does not rely on hardware extensions, such as ECC-protected memory. In my thesis I describe how to efficiently implement replication as a form of redundant multithreading in software. I develop mechanisms to manage replica resources and to make multi-threaded programs behave deterministically for replication.
I furthermore present an approach to handle applications that use shared-memory channels with other programs. My evaluation shows that Romain provides 100% error detection and more than 99.6% error correction for single-bit flips in memory and general-purpose registers. At the same time, Romain's execution time overhead is below 14% for single-threaded applications running in triple-modular redundant mode. The last part of my thesis acknowledges that software-implemented fault tolerance methods often rely on the correct functioning of a certain set of hardware and software components, the Reliable Computing Base (RCB).
I introduce the concept of the RCB and discuss what constitutes the RCB of the ASTEROID system and other fault tolerance mechanisms. Thereafter I show three case studies that evaluate approaches to protecting RCB components and thereby aim to achieve a software stack that is fully protected against hardware errors
Compiling and optimizing spreadsheets for FPGA and multicore execution
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007."September 2007."Includes bibliographical references (p. 102-104).A major barrier to developing systems on multicore and FPGA chips is an easy-to-use development environment. This thesis presents the RhoZeta spreadsheet compiler and Catalyst optimization system for programming multiprocessors and FPGAs. Any spreadsheet frontend may be extended to work with RhoZeta's multiple interpreters and behavioral abstraction mechanisms. RhoZeta synchronizes a variety of cell interpreters acting on a global memory space. RhoZeta can also compile a group of cells to multithreaded C or Verilog. The result is an easy-to-use interface for programming multicore microprocessors and FPGAs. A spreadsheet environment presents parallelism and locality issues of modem hardware directly to the user and allows for a simple global memory synchronization model. Catalyst is a spreadsheet graph rewriting system based on performing behaviorally invariant guarded atomic actions while a system is being interpreted by RhoZeta. A number of optimization macros were developed to perform speculation, resource sharing and propagation of static assignments through a circuit. Parallelization of a 64-bit serial leading-zero-counter is demonstrated with Catalyst. Fault tolerance macros were also developed in Catalyst to protect against dynamic faults and to offset costs associated with testing semiconductors for static defects. A model for partitioning, placing and profiling spreadsheet execution in a heterogeneous hardware environment is also discussed. The RhoZeta system has been used to design several multithreaded and FPGA applications including a RISC emulator and a MIDI controlled modular synthesizer.by Amir Hirsch.M.Eng
Integration of analysis techniques in security and fault-tolerance
This thesis focuses on the study of integration of formal methodologies in security protocol analysis and fault-tolerance analysis. The research is developed in two different directions: interdisciplinary and intra-disciplinary. In the former, we look for a beneficial interaction between strategies of analysis in security protocols and fault-tolerance; in the latter, we search for connections among different approaches of analysis within the security area. In the following we summarize the main results of the research
Virtual Runtime Application Partitions for Resource Management in Massively Parallel Architectures
This thesis presents a novel design paradigm, called Virtual Runtime Application Partitions (VRAP), to judiciously utilize the on-chip resources. As the dark silicon era approaches, where the power considerations will allow only a fraction chip to be powered on, judicious resource management will become a key consideration in future designs. Most of the works on resource management treat only the physical components (i.e. computation, communication, and memory blocks) as resources and manipulate the component to application mapping to optimize various parameters (e.g. energy efficiency). To further enhance the optimization potential, in addition to the physical resources we propose to manipulate abstract resources (i.e. voltage/frequency operating point, the fault-tolerance strength, the degree of parallelism, and the configuration architecture). The proposed framework (i.e. VRAP) encapsulates methods, algorithms, and hardware blocks to provide each application with the abstract resources tailored to its needs. To test the efficacy of this concept, we have developed three distinct self adaptive environments: (i) Private Operating Environment (POE), (ii) Private Reliability Environment (PRE), and (iii) Private Configuration Environment (PCE) that collectively ensure that each application meets its deadlines using minimal platform resources. In this work several novel architectural enhancements, algorithms and policies are presented to realize the virtual runtime application partitions efficiently. Considering the future design trends, we have chosen Coarse Grained Reconfigurable Architectures (CGRAs) and Network on Chips (NoCs) to test the feasibility of our approach. Specifically, we have chosen Dynamically Reconfigurable Resource Array (DRRA) and McNoC as the representative CGRA and NoC platforms. The proposed techniques are compared and evaluated using a variety of quantitative experiments. Synthesis and simulation results demonstrate VRAP significantly enhances the energy and power efficiency compared to state of the art.Siirretty Doriast
Resilient architecture (preliminary version)
The main objectives of WP2 are to define a resilient architecture and to develop a range of middleware solutions (i.e. algorithms, protocols, services) for resilience to be applied in the design of highly available, reliable and trustworthy networking solutions. This is the first deliverable within this work package, a preliminary version of the resilient architecture. The deliverable builds on previous results from WP1, the definition of a set of applications and use cases, and provides a perspective of the middleware services that are considered fundamental to address the dependability requirements of those applications. Then it also describes the architectural organisation of these services, according to a number of factors like their purpose, their function within the communication stack or their criticality/specificity for resilience. WP2 proposes an architecture that differentiates between two classes of services, a class including timeliness and trustworthiness oracles, and a class of so called complex services. The resulting architecture is referred to as a "hybrid architecture". The hybrid architecture is motivated and discussed in this document. The services considered within each of the service classes of the hybrid architecture are described. This sets the background for the work to be carried on in the scope of tasks 2.2 and 2.3 of the work package. Finally, the deliverable also considers high-level interfacing aspects, by providing a discussion about the possibility of using existing Service Availability Forum standard interfaces within HIDENETS, in particular discussing possibly necessary extensions to those interfaces in order to accommodate specific HIDENETS services suited for ad-hoc domain
Behind the last line of defense: Surviving SoC faults and intrusions
Today, leveraging the enormous modular power, diversity and flexibility of manycore systems-on-a-chip (SoCs) requires careful orchestration of complex and heterogeneous resources, a task left to low-level software, e.g., hypervisors. In current architectures, this software forms a single point of failure and worthwhile target for attacks: once compromised, adversaries can gain access to all information and full control over the platform and the environment it controls. This article proposes Midir, an enhanced manycore architecture, effecting a paradigm shift from SoCs to distributed SoCs. Midir changes the way platform resources are controlled, by retrofitting tile-based fault containment through well known mechanisms, while securing low-overhead quorum-based consensus on all critical operations, in particular privilege management and, thus, management of containment domains. Allowing versatile redundancy management, Midir promotes resilience for all software levels, including at low level. We explain this architecture, its associated algorithms and hardware mechanisms and show, for the example of a Byzantine fault tolerant microhypervisor, that it outperforms the highly efficient MinBFT by one order of magnitude