Computing a rectilinear shortest path amid splinegons in plane

We reduce the problem of computing a rectilinear shortest path between two given points s and t in the splinegonal domain \calS to the problem of computing a rectilinear shortest path between two points in the polygonal domain. As part of this, we define a polygonal domain \calP from \calS and transform a rectilinear shortest path computed in \calP to a path between s and t amid splinegon obstacles in \calS. When \calS comprises of h pairwise disjoint splinegons with a total of n vertices, excluding the time to compute a rectilinear shortest path amid polygons in \calP, our reduction algorithm takes O(n + h \lg{n}) time. For the special case of \calS comprising of concave-in splinegons, we have devised another algorithm in which the reduction procedure does not rely on the structures used in the algorithm to compute a rectilinear shortest path in polygonal domain. As part of these, we have characterized few of the properties of rectilinear shortest paths amid splinegons which could be of independent interest

Rectilinear Link Diameter and Radius in a Rectilinear Polygonal Domain

We study the computation of the diameter and radius under the rectilinear link distance within a rectilinear polygonal domain of $n$ vertices and $h$ holes. We introduce a \emph{graph of oriented distances} to encode the distance between pairs of points of the domain. This helps us transform the problem so that we can search through the candidates more efficiently. Our algorithm computes both the diameter and the radius in $\min \{\,O(n^\omega), O(n^2 + nh \log h + \chi^2)\,\}$ time, where $\omega<2.373$ denotes the matrix multiplication exponent and $\chi\in \Omega(n)\cap O(n^2)$ is the number of edges of the graph of oriented distances. We also provide a faster algorithm for computing the diameter that runs in $O(n^2 \log n)$ time

Computing Shortest Paths in the Plane with Removable Obstacles

We consider the problem of computing a Euclidean shortest path in the presence of removable obstacles in the plane. In particular, we have a collection of pairwise-disjoint polygonal obstacles, each of which may be removed at some cost c_i > 0. Given a cost budget C > 0, and a pair of points s, t, which obstacles should be removed to minimize the path length from s to t in the remaining workspace? We show that this problem is NP-hard even if the obstacles are vertical line segments. Our main result is a fully-polynomial time approximation scheme (FPTAS) for the case of convex polygons. Specifically, we compute an (1 + epsilon)-approximate shortest path in time O({nh}/{epsilon^2} log n log n/epsilon) with removal cost at most (1+epsilon)C, where h is the number of obstacles, n is the total number of obstacle vertices, and epsilon in (0, 1) is a user-specified parameter. Our approximation scheme also solves a shortest path problem for a stochastic model of obstacles, where each obstacle\u27s presence is an independent event with a known probability. Finally, we also present a data structure that can answer s-t path queries in polylogarithmic time, for any pair of points s, t in the plane

Planar rectilinear shortest path computation using corridors

AbstractThe rectilinear shortest path problem can be stated as follows: given a set of m non-intersecting simple polygonal obstacles in the plane, find a shortest L1-metric (rectilinear) path from a point s to a point t that avoids all the obstacles. The path can touch an obstacle but does not cross it. This paper presents an algorithm with time complexity O(n+m(lgn)3/2), which is close to the known lower bound of Ω(n+mlgm) for finding such a path. Here, n is the number of vertices of all the obstacles together

Routing for analog chip designs at NXP Semiconductors

During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP. This resulted in an heuristic approach, which we presented at the end of the week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach