Models predicting the performance of IC component or PCB channel during electromagnetic interference

This dissertation is composed of three papers, which cover the prediction of the characteristics of jitter due to crosstalk and due to simultaneous switching noise, and covers susceptibility of delay locked loop (DLL) to electromagnetic interference. In the first paper, an improved tail-fit de-convolution method is proposed for characterizing the impact of deterministic jitter in the presence of random jitter. A Wiener filter de-convolution method is also presented for extracting the characteristics of crosstalk induced jitter from measurements of total jitter made when the crosstalk sources were and were not present. The proposed techniques are shown to work well both in simulations and in measurements of a high-speed link. In the second paper, methods are developed to predict the statistical distribution of timing jitter due to dynamic currents drawn by an integrated circuit (IC) and the resulting power supply noise on the PCB. Distribution of dynamic currents is found through vectorless methods. Results demonstrate the approach can rapidly determine the average and standard deviation of the power supply noise voltage and the peak jitter within 5~15% error, which is more than sufficient for predicting the performance impact on integrated circuits. In the third paper, a model is developed to predict the susceptibility of a DLL to electromagnetic noise on the power supply. With the proposed analytical noise transfer function, peak to peak jitter and cycle to cycle jitter at the DLL output can be estimated, which can be use to predict when soft failures will occur and to better understand how to fix these failures. Simulation and measurement results demonstrate the accuracy of the DLL delay model. --Abstract, page iv

Method for dynamic power monitoring on FPGAs

International audienceThe ever-increasing integration densities make it possible to configure multi-core systems composed of hundreds of blocks on existing FPGAs that may influence overall consumption differently. Observing total consumption is not sufficient to accurately assess internal circuit activity to be able to deploy effective adaptation strategies. In this case monitoring techniques are required. This paper presents a CAD flow for high-level dynamic power estimation on FPGAs. The method is based on the monitoring of toggling activity for relevant signals by introducing event counters. The appropriate signals are selected using the Greedy Stepwise filter. Our approach is based on a generic method that is able to produce a power model for any block-based circuit. We evaluated our contribution on a SoC RTL model implemented on Spartan3, Virtex5, and Spartan6 FPGAs. A power model and monitors are automatically generated to achieve the best tradeoff between accuracy and overhead

LeakyOhm: Secret Bits Extraction using Impedance Analysis

The threats of physical side-channel attacks and their countermeasures have been widely researched. Most physical side-channel attacks rely on the unavoidable influence of computation or storage on current consumption or voltage drop on a chip. Such data-dependent influence can be exploited by, for instance, power or electromagnetic analysis. In this work, we introduce a novel non-invasive physical side-channel attack, which exploits the data-dependent changes in the impedance of the chip. Our attack relies on the fact that the temporarily stored contents in registers alter the physical characteristics of the circuit, which results in changes in the die's impedance. To sense such impedance variations, we deploy a well-known RF/microwave method called scattering parameter analysis, in which we inject sine wave signals with high frequencies into the system's power distribution network (PDN) and measure the echo of the signals. We demonstrate that according to the content bits and physical location of a register, the reflected signal is modulated differently at various frequency points enabling the simultaneous and independent probing of individual registers. Such side-channel leakage challenges the $t$-probing security model assumption used in masking, which is a prominent side-channel countermeasure. To validate our claims, we mount non-profiled and profiled impedance analysis attacks on hardware implementations of unprotected and high-order masked AES. We show that in the case of the profiled attack, only a single trace is required to recover the secret key. Finally, we discuss how a specific class of hiding countermeasures might be effective against impedance leakage

Hardware-in-the-Loop Platform for Assessing Battery State Estimators in Electric Vehicles

The development of new algorithms for the management and state estimation of lithiumion batteries requires their verification and performance assessment using different approaches and tools. This paper aims at presenting an advanced hardware in the loop platform which uses an accurate model of the battery to test the functionalities of battery management systems (BMSs) in electric vehicles. The developed platform sends the simulated battery data directly to the BMS under test via a communication link, ensuring the safety of the tests. As a case study, the platform has been used to test two promising battery state estimators, the Adaptive Mix Algorithm and the Dual Extended Kalman Filter, implemented on a field-programmable gate array based BMS. Results show the importance of the assessment of these algorithms under different load profiles and conditions of the battery, thus highlighting the capabilities of the proposed platform to simulate many different situations in which the estimators will work in the target application

Fault Diagnosis and Condition Monitoring of Power Electronic Components Using Spread Spectrum Time Domain Reflectometry (SSTDR) and the Concept of Dynamic Safe Operating Area (SOA)

Title from PDF of title page viewed April 1, 2021Dissertation advisors: Faisal Khan and Yong ZengVitaIncludes bibliographical references ( page 117-132)Thesis (Ph.D.)--School of Computing and Engineering and Department of Mathematics and Statistics. University of Missouri--Kansas City, 2021Fault diagnosis and condition monitoring (CM) of power electronic components with a goal of improving system reliability and availability have been one of the major focus areas in the power electronics field in the last decades. Power semiconductor devices such as metal oxide semiconductor field-effect transistor (MOSFET) and insulated-gate bipolar transistor (IGBT) are considered to be the most fragile element of the power electronic systems and their reliability degrades with time due to mechanical and thermo-electrical stresses, which ultimately leads to a complete failure of the overall power conversion systems. Therefore, it is important to know the present state of health (SOH) of the power devices and the remaining useful life (RUL) of a power converter in order to perform preventive scheduled maintenance, which will eventually lead to increased system availability and reduced cost. In conventional practice, device aging and lifetime prediction techniques rely on the estimation of the meantime to failure (MTTF), a value that represents the expected lifespan of a device. MTTF predicts expected lifespan, but cannot adequately predict failures attributed to unusual circumstances or continuous overstress and premature degradation. This inability is due in large part to the fact that it considers the device safe operating area (SOA) or voltage and current ride-through capability to be independent of SOH. However, we experimentally proved that SOA of any semiconductor device goes down with the increased level of aging, and therefore, the probability of occurrence of over-voltage/current situation increases. As a result, the MTTF of the device as well as the overall converter reliability reduces with aging. That said, device degradation can be estimated by accomplishing an accurate online degradation monitoring tool that will determine the dynamic SOA. The correlation between aging and dynamic SOA gives us the useful remaining life of the device or the availability of a circuit. For this monitoring tool, spread spectrum time domain reflectometry (SSTDR) has been proposed and was successfully implemented in live power converters. In SSTDR, a high-frequency sine-modulated pseudo-noise sequence (SMPNS) is sent through the system, and reflections from age-related impedance discontinuities return to the test end where they are analyzed. In the past, SSTDR has been successfully used for device degradation detection in power converters while running at static conditions. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast-switching operation makes CM more challenging while using SSTDR. The algorithms and techniques developed in this project have overcome this challenge and demonstrated that the SSTDR test data are consistent with the aging of the power devices and do not affect the switching performance of the modulation process even the test signal is applied across the gate-source interface of the power MOSFET. This implies that the SSTDR technique can be integrated with the gate driver module, thereby creating a new platform for an intelligent gate-driver architecture (IGDA) that enables real-time health monitoring of power devices while performing features offered by a commercially available driver. Another application of SSTDR in power electronic systems is the ground fault prediction and detection technique for PV arrays. Protecting PV arrays from ground faults that lead to fire hazards and power loss is imperative to maintaining safe and effective solar power operations. Unlike many standard detection methods, SSTDR does not depend on fault current, therefore, can be implemented for testing ground faults at night or low illumination. However, wide variation in impedance throughout different materials and interconnections makes fault location more challenging than fault detection. This barrier was surmounted by the SSTDR-based fault detection algorithm developed in this project. The proposed algorithm was accounted for any variation in the number of strings, fault resistance, and the number of faults. In addition to its general utility for fault detection, the proposed algorithm can identify the location of multiple faults using only a single measurement point, thereby working as a preventative measure to protect the entire system at a reduced cost. Within the scope of the research work on SSTDR-based fault diagnosis and CM of power electronic components, a cell-level SOH measurement tool has been proposed that utilizes SSTDR to detect the location and aging of individual degraded cells in a large series-parallel connected Li-ion battery pack. This information of cell level SOH along with the respective cell location is critical to calculating the SOH of a battery pack and its remaining useful lifetime since the initial SOH of Li-ion cells varies under different manufacturing processes and operating conditions, causing them to perform inconsistently and thereby affect the performance of the entire battery pack in real-life applications. Unfortunately, today’s BMS considers the SOH of the entire battery pack/cell string as a single SOH and therefore, cannot monitor the SOH at the cell level. A healthy battery string has a specific impedance between the two terminals, and any aged cell in that string will change the impedance value. Since SSTDR can characterize the impedance change in its propagation path along with its location, it can successfully locate the degraded cell in a large battery pack and thereby, can prevent premature failure and catastrophic danger by performing scheduled maintenance.Introduction -- Background study and literature review -- Fundamentals of Spread Spectrum Time Domain Reflectometry (SSTDR): A new method for testing electronics live -- Accelerated aging test bench: design and implementation -- Condition monitoring of power switching in live power switching devices in live power electronic converters using SSTDR -- An irradiance-independent, robust ground-fault detection scheme for PV arrays based on SSTDR -- Detection of degraded/aged cell in a LI-Ion battery pack using SSTDR -- Dynamiv safe operating area (SOA) of power semiconductor devices -- Conclusion and future researc

Advances in Li-Ion battery management for electric vehicles

This paper aims at presenting new solutions for advanced Li-Ion battery management to meet the performance, cost and safety requirements of automotive applications. Emphasis is given to monitoring and controlling the battery temperature, a parameter which dramatically affects the performance, lifetime, and safety of Li-Ion batteries. In addition to this, an innovative battery management architecture is introduced to facilitate the development and integration of advanced battery control algorithms. It exploits the concept of smart cells combined with an FPGA-based centralized unit. The effectiveness of the proposed solutions is shown through hardware-in-the-loop simulations and experimental results

Degradation in FPGAs: Monitoring, Modeling and Mitigation

This dissertation targets the transistor aging degradation as well as the associated thermal challenges in FPGAs (since there is an exponential relation between aging and chip temperature). The main objectives are to perform experimentation, analysis and device-level model abstraction for modeling the degradation in FPGAs, then to monitor the FPGA to keep track of aging rates and ultimately to propose an aging-aware FPGA design flow to mitigate the aging

Prognostic System for Power Modules in Converter Systems Using Structure Function

This paper proposes an on-board methodology for monitoring the health of power converter modules in drive systems, using vector control heating and structure function to check for degradation. It puts forward a system that is used on-board to measure the cooling curve and derive the structure function during idle times for maintenance purposes. The structure function is good tool for tracking the magnitude and location of degradation in power modules. The ability to keep regular track of the actual degradation level of the modules enables the adoption of preventive maintenance, reducing or even eliminating altogether the appearance of failures during operation, significantly improving the availability of the power devices. The novelty in this work is the complete system that is used to achieve degradation monitoring; combining the heating technique and the measurement without additional power components except the measurement circuit which can be integrated into the gate drive board and the challenges encountered. Experimental results obtained from this show that it is possible to implement an on-board health monitoring system in converters which measures the degradation on power modules

Bioimpedance sensor and methodology for acute pain monitoring

The paper aims to revive the interest in bioimpedance analysis for pain studies in communicating and non-communicating (anesthetized) individuals for monitoring purpose. The plea for exploitation of full potential offered by the complex (bio)impedance measurement is emphasized through theoretical and experimental analysis. A non-invasive, low-cost reliable sensor to measure skin impedance is designed with off-the-shelf components. This is a second generation prototype for pain detection, quantification, and modeling, with the objective to be used in fully anesthetized patients undergoing surgery. The 2D and 3D time-frequency, multi-frequency evaluation of impedance data is based on broadly available signal processing tools. Furthermore, fractional-order impedance models are implied to provide an indication of change in tissue dynamics correlated with absence/presence of nociceptor stimulation. The unique features of the proposed sensor enhancements are described and illustrated here based on mechanical and thermal tests and further reinforced with previous studies from our first generation prototype