From FPGA to ASIC: A RISC-V processor experience

This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

Simulation of Multi-element Antenna Systems for Navigation Applications

The application of user terminals with multiple antenna inputs for use with the global satellite navigation systems like GPS and Galileo becomes more and more attraction in last years. Multiple antennas may be spread over the user platform and provide signals required for the platform attitude estimation or may be arranged in an antenna array to be used together with array processing algorithms for improving signal reception, e.g. for multipath and interference mitigation. In order to generate signals for testing of receivers with multiple antenna inputs and corresponding receiver algorithms in a laboratory environment a unique HW signal simulation tool for wavefront simulation has been developed. The signals for a number of antenna elements in a flexible user defined geometry are first generated as digital signals in baseband and then mixed up to individual RF-outputs. The paper describes the principle function of the system and addresses some calibration issues. Measurement set-ups and results of data processing with simulated signals for different applications are shown and discussed